DS2180A DS2180A T1 Transceiver PIN ASSIGNMENT • Single chip DS1 rate transceiver • Supports common framing standards – 12 frames/superframe “193S” – 24 frames/superframe “193E” TMSYNC 1 40 VDD TFSYNC 2 39 RLOS TCLK 3 38 RFER TCHCLK 4 37 RBV TSER 5 36 RCL TMO 6 35 RNEG TSIGSEL 7 RPOS TSIGFR TABCD 8 9 34 33 32 TEST TLINK 10 31 RSIGSEL TLCLK 11 30 RSIGFR TPOS 12 29 RABCD TNEG 13 28 RMSYNC INT 14 27 RFSYNC SDI 26 RSER SDO 15 16 25 RCHCLK CS 17 24
DS2180A Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides output clocks useful for data conditioning and decoding.
DS2180A TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY) Table 1 PIN SYMBOL TYPE DESCRIPTION 1 TMSYNC I Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to reinforce multiframe alignment or tied low, which allows internal multiframe counter to free run. 2 TFSYNC I Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed every frame to reinforce internal frame counter or tied low (allowing TMSYNC to establish frame and multiframe alignment).
DS2180A POWER AND TEST PIN DESCRIPTION (40–PIN DIP ONLY) Table 3 PIN SYMBOL TYPE DESCRIPTION 20 VSS – Signal Ground. 0.0 volts. 32 TEST I Test Mode. Tie to VSS for normal operation. 40 VDD – Positive Supply. 5.0 volts. RECEIVE PIN DESCRIPTION (40–PIN DIP ONLY) Table 4 PIN SYMBOL TYPE DESCRIPTION 21 RYEL O Receive Yellow Alarm. Transitions high when yellow alarm detected, goes low when alarm clears. 22 RLINK O Receive Link Data.
DS2180A REGISTER SUMMARY Table 5 REGISTER ADDRESS T/R1 RSR 0000 R2 Receive Status Register. Reports all receive alarm conditions. RIMR 0001 R Receive Interrupt Mask Register. Allows masking of individual alarm-generated interrupts. BVCR 0010 R Bipolar Violation Count Register. 8-bit presettable counter which records individual bipolar violations. ECR 0011 R Error Count Register. Two independent 4-bit counters which record OOF occurrences and individual frame bit or CRC errors.
DS2180A DATA I/O BURST MODE Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into the addressed register on the rising edges of the next eight SCLK cycles. Following an address/command word to read, contents of the selected register are output on the falling edges of the next eight SCLK cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where the host processor has a bidirectional I/O pin.
DS2180A COMMON CONTROL REGISTER Figure 4 (MSB) (LSB) FRSR2 – EYELMD FM SYELMD B8ZS B7 LPBK SYMBOL POSITION NAME AND DESCRIPTION – CCR.7 Reserved, must be 0 for proper operation. FRSR2 CCR.6 Function of REC Status Register 2. 0 = Detected B8ZS code words reported at RSR.2. 1 = COFA (Change-of-Frame Alignment) reported at RSR.2 when last resync resulted in change of frame or multiframe alignment. EYELMD CCR.5 193E Yellow Mode Select.
DS2180A B8ZS The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding maintains system 1’s density requirements without disturbing data integrity as required in emerging clear channel applications. B8ZS coding replaces eight consecutive outgoing 0’s with a B8ZS code word. Any received B8ZS code word is replaced with all 0’s. B8ZS and bit 7 stuffing modes should not be enabled simultaneously. Enabling both results in LOS.
DS2180A TRANSMIT SIGNALING When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S) or in frames 6, 12, 18 and 24 (193E) in the 8th bit position of every channel word. Signaling data is sampled at TABCD on the falling edge of TCLK during bit 8 of each input word during signaling frames. Logical combination of clocks TMO, TSIGFR and TSIGSEL allows external multiplexing of separate serial links for A, B or A, B, C, D signaling sources.
DS2180A TRANSMIT INSERTION HIERARCHY Figure 8 TSER TLINK TABCD F-BIT TSER IDLE Y N TSER Y TSER Y IDLE CLEAR CLEAR N N TSER IDLE SIG SIG N Y IDLE Y N TSER + ABCD TSER Y Y B7 STUFF B7 STUFF N TSER + ABCD + B7 N TSER + ABCD TSER + B7 TSER 193S YELLOW ALARM – B2 STUFF B8ZS BLUE or LPBK TPOS, TNEG 041995 10/36 IDLE IDLE + ABCD
DS2180A 193S TRANSMIT MULTIFRAME TIMING Figure 9 FRAME # 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 TFSYNC TMSYNC1 TMO1 TSIGSEL TSIGFR TLCLK TABCD2 TLINK3 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ B A B A NOTES: 1. Transmit frame and multiframe timing may be established in one of four ways: a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish multiframe boundaries, allowing internal counters to determine frame timing. b.
DS2180A 193E TRANSMIT MULTIFRAME TIMING Figure 10 FRAME # 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 TFSYNC TMSYNC1 TMO1 TSIGSEL TSIGFR TLCLK TABCD2 ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉ D A B C D TLINK3 NOTES: 1. Transmit frame and multiframe timing may be established in one of four ways: a.
DS2180A TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11 TCLK TMSYNC TMO TFSYNC TSIGSEL TSIGFR TLCLK TCHCLK TLINK1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ TABCD TSER2 LSB MSB LSB F MSB LSB MSB TPOS, TNEG LSB MSB LSB MSB LSB F MSB NOTES: 1. TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated for insertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is sampled during even frames. 2. If TCR.
DS2180A RECEIVE CONTROL REGISTER Figure 12 (MSB) ARC (LSB) OOF RCI RCS SYNCC SYNCT SYNCE RESYNC SYMBOL POSITION NAME AND DESCRIPTION ARC RCR.7 Auto Resync Criteria. 0 = Resync on OOF or RCL event. 1 = Resync on OOF only. OOF RCR.6 Out-of-frame (OOF) Condition Detection. 0 = 2 of 4 framing bits in error. 1 = 2 of 5 framing bits in error. RCI RCR.5 Receive Code Insert. When set, the receive code selected by RCR.4 is inserted into channels marked by RMR registers.
DS2180A RECEIVE SIGNALING coming channels. Logical combination of clocks RMSYNC, RSIGFR and RSIGSEL allow the user to identify and extract AB or ABCD signaling data.
DS2180A 193E RECEIVE MULTIFRAME TIMING Figure 15 FRAME# 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RFSYNC RMSYNC RSIGSEL RSIGFR RLCLK RABCD1 RLINK2 ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ D A B C D NOTES: 1. Signaling data is updated during signaling frames on channel boundaries. RABCD outputs the LSB of each channel word in non-signaling frames. 2. RLINK data (FDL-bit) is updated one bit time prior to odd frames and held for two frames.
DS2180A RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 RCLK RPOS,2 RNEG LSB F MSB LSB MSB LSB MSB RFSYNC RMSYNC RSIGSEL RSIGFR RLCLK RCHCLK RLINK1 RABCD CHANNEL 23 B OR D CHANNEL 24 B OR D RSER LSB MSB LSB F MSB LSB MSB NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
DS2180A RSR: RECEIVE STATUS REGISTER Figure 17 (MSB) BVCS (LSB) ECS RYEL RCL FERR B8ZSD RBL RLOS SYMBOL POSITION NAME AND DESCRIPTION BVCS RSR.7 Bipolar Violation Count Saturation. Set when the 8-bit counter at BVCR saturates. ECS RSR.6 Error Count Saturation. Set when either of the 4-bit counters at ECR saturates. RYEL RSR.5 Receive Yellow Alarm. Set when yellow alarm detected. (Detected yellow alarm format determined by CCR.4 and CCR.3.) RCL RSR.4 Receive Carrier Loss.
DS2180A RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18 (MSB) BVCS (LSB) ECS RYEL RCL FERR B8ZSD SYMBOL POSITION BVCS RIMR.7 Bipolar Violation Count Saturation Mask. 1 = Interrupt masked. 0 = Interrupt masked. ECS RIMR.6 Error Count Saturation Mask. 1 = Interrupt enabled. 0 = Interrupt masked. RYEL RIMR.5 Receive Yellow Alarm Mask. 1 = Interrupt enabled. 0 = Interrupt masked. RCL RIMR.4 Receive Carrier Loss Mask. 1 = Interrupt enabled. 0 = Interrupt masked. FERR RIMR.
DS2180A BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19 (MSB) BVD7 (LSB) BVD6 BVD5 BVD4 BVD3 SYMBOL POSITION BVD7 BVCR.7 MSB of bipolar count. BVD0 BVCR.0 LSB of bipolar count. BVD2 BVD1 BVD0 NAME AND DESCRIPTION This 8-bit binary up counter saturates at 255 and will generate an interrupt for each occurrence of a bipolar violation once saturated (RIMR.7=1). Presetting this register allows the user to establish specific count interrupt thresholds.
DS2180A RYEL OUTPUT RFER OUTPUT The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates the alarm condition has been cleared. The RYEL bit (RSR.5) is a “latched” version of the RYEL output. In 193E framing, the yellow alarm pattern detected is 16 pattern sets of 00 (Hex) and FF (Hex) received at RLINK. In 193S, framing the yellow alarm format is dependent on CCR.3; if CCR.
DS2180A HARDWARE MODE For preliminary system prototyping or applications which do not require the features offered by the serial port, the transceiver can be reconfigured by the SPS pin. Tying SPS to VSS disables the serial port, clears all internal registers except CCR and TCR and redefines pins 14 through 18 as mode control inputs. The hardware mode allows device retrofit into existing applications where mode control and alarm conditioning hardware is often designed with discrete logic.
DS2180A T1 OVERVIEW Framing Standards The DS2180A is compatible with the existing Bell System D4 framing standard described in ATT PUB 43801 and the new extended superframe format (ESF) as described in ATT C.B. #142. In this document, D4 framing is referred to as 193S and ESF (also known as Fe) is referred to as 193E. Programmable features of the DS2180A allow support of other framing standards which are derivatives of 193E and 193S.
DS2180A 193E FRAMING FORMAT Table 7 F-BIT USE BIT USE IN EACH CHANNEL FRAME NUMBER FPS1 FDL2 1 – M – BITS 1–8 2 – – C1 BITS 1–8 3 – M – BITS 1–8 4 0 – – BITS 1–8 5 – M – BITS 1–8 6 – – C2 BITS 1–7 7 – M – BITS 1–8 8 0 – – BITS 1–8 CRC3 DATA 9 – M – BITS 1–8 10 – – C3 BITS 1–8 11 – M – BITS 1–8 12 1 – – BITS 1–7 13 – M – BITS 1–8 14 – – C4 BITS 1–8 15 – M – BITS 1–8 16 0 – – BITS 1–8 17 – M – BITS 1–8 18 – – C5 B
DS2180A 193S FRAMING FORMAT Table 8 F-BIT USE FRAME NUMBER BIT USE IN EACH CHANNEL SIGNALING-BIT USE FT1 FS2 1 1 – BITS 1–8 2 – 0 BITS 1–8 3 0 – BITS 1–8 4 – 0 BITS 1–8 5 1 – BITS 1–8 6 – 1 BITS 1–7 7 0 – BITS 1–8 8 – 1 BITS 1–8 DATA 9 1 – BITS 1–8 10 – 1 BITS 1–8 11 0 – BITS 1–8 12 – 03 BITS 1–7 SIGNALING4 BIT 8 A BIT 8 B NOTES: 1. FT (terminal framing) bits provide frame alignment information. 2.
DS2180A TRANSMIT SIDE OVERVIEW The transmit side of the DS2180A is made up of six major functional blocks: timing and clock generation, data selector, bipolar coder, yellow alarm, F-bit data and CRC. The timing and clock generation circuit develops all onboard and output clocks to the system from inputs TCLK, TFSYNC, and TMSYNC. The yellow alarm circuitry generates mode–dependent yellow alarms. The CRC block generates checksum results utilized in 193E framing.
DS2180A low, and a false multiframe position may be indicated by RMSYNC. RFER will indicate when the received S-bit pattern does not match the assumed internal multiframe alignment. This mode will be used in applications where non-standard S-bit patterns exist. In such applications, multiframe alignment information can be decoded externally by using the S-bits present at RLINK. nizer before sync is declared. Clearing RCR.3 causes the synchronizer to search for FT patterns (101010...
DS2180A BACKPLANE INTERFACE USING DS2180A AND DS2176 Figure 22 RECEIVE LINE INTERFACE DS2187 TPOS TNEG RPOS RNEG TSIGSEL TSIGFR TCHCLK TABCD TSER TCLK TMO TFSYNC SIGNALING TRANSMIT BACKPLANE INTERFACE CONTROL VDD SPS RLCLK TLCLK RLINK TLINK TMSYNC TEST VSS RCLK RMSYNC RSER RFER RLOS RCLK RMSYNC RSER SMO SIGH SM1 SLIP INT RST SDI SCLK CS SDO FMS ALN SCLKSEL VSS DS2180A VDD S/P A B C D SSER SYSCLK SFSYNC SMSYNC DS2176 DATA LINK SUPERVISION 041995 28/36 PCM HOST CONTROLLER 1.
DS2180A PROCESSOR-BASED TRANSMIT SIGNALING INSERTION Figure 23 8031/51 DS2180A 19 14 INT0 12 16 RXD TXD P1.0 10 15 11 18 1 17 SPS INT SDO SDI SCLK CS TPOS 8 P1.1 2 3 4 5 6 7 INT1 SI SO D0 Q0 D1 CY7C401 (64 x 4 FIFO) Q1 D2 Q2 D3 Q3 MR 15 13 4 9 TSIGFR TNEG TCHCLK TABCD 12 11 10 1 2 TMSYNC TFSYNC 13 Multiframe Sync PROCESSOR-BASED SIGNALING Many robbed-bit signaling applications utilize a microprocessor to insert transmit signaling data into the outgoing data stream.
DS2180A ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to 7.0V 0°C to +70°C –55°C to 125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DS2180A AC ELECTRICAL CHARACTERISTICS PARAMETER (0°C to 70°C; VDD = 5V + 10%) SYMBOL MIN SDI to SCLK Setup tDC 50 ns SCLK to SDI Hold tCDH 50 ns SDI to SCLK Falling Edge tCD 50 ns SCLK Low Time tCL 250 ns SCLK High Time tCH 250 ns SCLK Rise & Fall Time TYP MAX tR, tF 500 UNITS NOTES ns CS to SCLK Setup tCC 50 ns SCLK to CS Hold tCCH 50 ns CS Inactive Time tCWH 250 SCLK to SDO Valid2 tCDV 200 ns CS to SDO High Z tCDZ 75 ns SCLK Setup to CS Falling tSCC ns
DS2180A SERIAL PORT READ AC TIMING CS tCDZ SCLK tCDV High Z SDO NOTE: 1. Serial port write must precede a port read to provide address information.
DS2180A AC ELECTRICAL CHARACTERISTICS1 – RECEIVE PARAMETER SYMBOL MIN (0°C to 70°C; VDD = 5V + 10%) TYP MAX UNITS Propagation Delay RCLK to RMSYNC, RFSYNC, RSIGSEL, RSIGFR, RLCLK, RCHCLK tPRS 75 ns Propagation Delay RCLK to RSER, RABCD, RLINK tPRD 75 ns Transition Time All Outputs tTTR 20 ns RCLK Period RCLK Pulse Width tP 250 648 ns tWL, tWH 125 324 ns 20 ns RCLK Rise & Fall Times tR, tF RPOS, RNEG Setup to RCLK Falling tSRD 50 ns RPOS, RNEG Hold to RCLK Falling tHRD 5
DS2180A TRANSMIT AC TIMING DIAGRAM tP tWH tF tWL tR TCLK tSTD tHTD TSER, TABCD, TLINK tSTS tTSP TFSYNC, TMSYNC tPTS TMO, TLCLK, TSIGSEL, TSIGFR tPTCH TCHCLK, TPOS, TNEG RECEIVE AC TIMING DIAGRAM tP tWH RCLK tPRD RSER, RABCD, RLINK RMSYNC,RFSYNC, RSIGSEL, RSIGFR, RLCLK, RCHCLK tPRS tPRA RYEL, RCL, RBV, RFER, RLOS tRST RST tSRD RPOS, RNEG 041995 34/36 tHRD tWL tF tR
DS2180A DS2180A SERIAL T1 TRANSCEIVER (600 MIL DIP) B D 1 A E C F K G J H INCHES DIM. MIN. MAX. A 2.050 2.075 B 0.530 0.550 C 0.140 0.160 D 0.600 0.625 E 0.015 0.040 F 0.120 0.145 G 0.090 0.110 H 0.625 0.675 J 0.008 0.012 K 0.015 0.
DS2180A DS2180AQ SERIAL T1 TRANSCEIVER (PLCC) E E1 B N 1 .075 MAX D1 D D2 NOTE 1 B1 CH1 .150 MAX e1 C E2 A2 NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM. MIN. MAX. A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 CH1 0.042 0.048 D 0.685 0.695 D1 0.650 0.656 D2 0.590 0.630 E 0.685 0.695 E1 0.650 0.656 E2 0.590 0.630 e1 N 041995 36/36 0.
