User Manual

DS2172
031197 13/20
SR: STATUS REGISTER (Address=14 Hex)
(MSB) (LSB)
–
RA1 RA0 RLOS BED BCOF BECOF SYNC
SYMBOL POSITION NAME AND DESCRIPTION
– SR.7 Not Assigned. Could be any value when read.
RA1 SR.6 Receive All Ones. Set when 32 consecutive ones are received; allowed to
be cleared when a zero is received.
RA0 SR.5 Receive All Zeros. Set when 32 consecutive zeros are received; allowed
to be cleared when a one is received.
RLOS SR.4 Receive Loss Of Sync. Set when the device is searching for synchroniza-
tion. Once sync is achieved, will remain set until read.
BED SR.3 Bit Error Detection. Set when bit errors are detected.
BCOF SR.2 Bit Counter Overflow. Set when the 32–bit BCR overflows.
BECOF SR.1 Bit Error Count Overflow. Set when the 32–bit BECR overflows.
SYNC SR.0 Sync. Real time status of the synchronizer (this bit is not latched). Will be
set when the incoming pattern at RDATA matches for 32 consecutive bit
positions. Will be cleared when 6 or more bits out of 64 are received in error
(if PCR.2 = 0).
IMR: INTERRUPT MASK REGISTER (Address=15 Hex)
(MSB) (LSB)
– RA1 RA0 RLOS BED BCOF BECOF SYNC
SYMBOL POSITION NAME AND DESCRIPTION
– IMR.7 Not Assigned. Should be set to zero when written to.
RA1 IMR.6 Receive All Ones.
0 = interrupt masked
1 = interrupt enabled
RA0 IMR.5 Receive All Zeros.
0 = interrupt masked
1 = interrupt enabled
RLOS IMR.4 Receive Loss Of Sync.
0 = interrupt masked
1 = interrupt enabled
BED IMR.3 Bit Error Detection.
0 = interrupt masked
1 = interrupt enabled
BCOF IMR.2 Bit Counter Overflow .
0 = interrupt masked
1 = interrupt enabled
BECOF IMR.1 Bit Error Count Overflow.
0 = interrupt masked
1 = interrupt enabled
SYNC IMR.0 Sync.
0 = interrupt masked
1 = interrupt enabled