Manual

DS2154
031197 3/69
DS2154 ENHANCED E1 SINGLE–CHIP TRANSCEIVER Figure 1–1
8
VCO / PLL
7
4 3
4
RCL RCLK RLOS 8MCLK RLINK RLCLK RCHBLK RCHCLK RSIGF RSIG RSER RSYSCLK RSYNC RMSYNC RFSYNC RDATA TSYNC TDATA TESO TSSYNC TSYSCLK TSER TSIG TCLK TCHBLK TCHCLK TLINK TLCLK
SIGNALING
BUFFER
8.182 MHz CLOCK
SYNTHESIZER
TIMING
CONTROL
Sa EXTRACTION
ELASTIC
STORE
SYNC CONTROL
HARDWARE
SIGNALING
INSERTION
ELASTIC
STORE
STIMING CONTROL
Sa INSERTION
LOTCMUX
SYNC
CLOCK DATA
SYNC
CLOCK DATA
RECEIVE SIDE
FRAMER
TRANSMIT
SIDE
FORMATTER
FRAMER LOOPBACK
REMOTE LOOPBACK
PER–CHANNEL CODE INSERT
FAS WORD INSERTION
SI BIT INSERTION
E–BIT INSERTION
SA INSERTION
PER–CHANNEL LOOPBACK
SIGNALING INSERTION
CRC4 GENERAITON
HDB3 ENCODE
AIS GENERAITON
PER–CHANNEL CODE INSERT
SA AND SI EXTRACTION
SIGNALING EXTRACTION
E–BIT COUNTER
FAS ERROR COUNTER
CRC ERROR COUNTER
ALARM DETECTION
SYNCHRONIZER
BPV COUNTER
HDB3 DECODER
LIUCMUX
JITTER ATTENUATION
(CAN BE PLACED IN EITHER
TRANSMIT OR RECEIVE PATH)
16.384 MHz
LOCAL LOOPBACK
POWER
CONNECTIONS
CLOCK/DATA
RECOVERY
PEAK
EQUALIZER
DETECT
LIU AIS
GENERATION
WAVE–
SHAPING
LINE
DRIVERS
PARALLEL AND TEST CONTROL PORT
(ROUTED TO ALL BLOCKS)
MUX
CLOCK/
CRYSTAL
INTERFACE
2.048
MHz
32.768 MHz
LIUC
TPOSO
TCLKO
TNEGO
TNEGI
TCLKI
TPOSI
MUX
D0 to D7/
AD0 to AD7
A0 to A6
ALE(AS)/A7
RD
(DS)
WR(R/W)
BTS
CS
TEST
INT
RPOSI
RCLKI
RNEGI
RNEGO
RCLKO
RPOSO
8XCLK
XTALD
MCLK
RVDD
DVDD
TVDD
RVSS
DVSS
TVSS
RRING
RTIP
TRING
TTIP
LOTC