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DS2154

Enhanced E1 Single Chip Transceiver

DS2154

PRELIMINARY

031197 1/69

FEATURES

• Complete E1(CEPT) PCM–30/ISDN–PRI transceiver

functionality

• Onboard long and short haul line interface for clock/

data recovery and waveshaping

• 32–bit or 128–bit crystal–less jitter attenuator

• Generates line build outs for both 120Ω and 75Ω lines

• Frames to FAS, CAS, and CRC4 formats

• Dual onboard two–frame elastic store slip buffers that

can connect to asynchronous backplanes up to

8.192 MHz

• 8–bit parallel control port that can be used directly on

either multiplexed or non–multiplexed buses

• Extracts and inserts CAS signaling

• Detects and generates Remote and AIS alarms

• Programmable output clocks for Fractional E1, H0,

and H12 applications

• Fully independent transmit and receive functionality

• Full access to both Si and Sa bits aligned with CRC

multiframe

• Four separate loopbacks for testing functions

• Large counters for bipolar and code violations, CRC4

codeword errors, FAS errors, and E bits

• Pin compatible with DS2152 T1 Enhanced Single–

Chip Transceiver

• 5V supply; low power CMOS

• 100–pin 14mm

body LQFP package

PACKAGE OUTLINE

100

ORDERING INFORMATION

DS2154L (0°C to 70°C)

DS2154LN (–40°C to +85°C)

DESCRIPTION

The DS2154 Enhanced Single–Chip Transceiver

(ESCT) contains all of the necessary functions for con-

nection to E1 lines. The device is an upward compatible

version of the DS2153 Single–Chip Transceiver. The

onboard clock/data recovery circuitry coverts the AMI/

HDB3 E1 waveforms to a NRZ serial stream. The

DS2154 automatically adjusts to E1 22AWG (0.6 mm)

twisted–pair cables from 0 to over 2km in length. The

device can generate the necessary G.703 waveshapes

for both 75 ohm coax and 120 ohm twisted cables. The

Summary of content (69 pages)

PAGE 1
DS2154 PRELIMINARY DS2154 Enhanced E1 Single Chip Transceiver FEATURES PACKAGE OUTLINE • Complete E1(CEPT) PCM–30/ISDN–PRI transceiver functionality • Onboard long and short haul line interface for clock/ data recovery and waveshaping • 32–bit or 128–bit crystal–less jitter attenuator • Generates line build outs for both 120Ω and 75Ω lines • Frames to FAS, CAS, and CRC4 formats • Dual onboard two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.
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DS2154 onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa bit information. The device contains a set of internal registers which the user can access and control the operation of the unit.
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DS2154 TCHBLK TCHCLK TLINK TLCLK Sa INSERTION TCLK SYNC CLOCK DATA MUX ELASTIC STORE LOTC HARDWARE SIGNALING INSERTION STIMING CONTROL TSSYNC TSYSCLK TSER TSIG TDATA TESO SYNC CONTROL ELASTIC STORE TIMING CONTROL Sa EXTRACTION SYNC CLOCK DATA TRANSMIT SIDE FORMATTER PER–CHANNEL CODE INSERT FAS WORD INSERTION SI BIT INSERTION E–BIT INSERTION SA INSERTION PER–CHANNEL LOOPBACK SIGNALING INSERTION CRC4 GENERAITON HDB3 ENCODE AIS GENERAITON FRAMER LOOPBACK LIUC RECEIVE SIDE FRAMER PER–CHANN
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DS2154 FUNCTIONAL DESCRIPTION The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS2154. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS2154 contains an active filter that reconstructs the analog received signal for the non–linear losses that occur in transmission.
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DS2154 PIN SYMBOL TYPE DESCRIPTION 9 NC – No Connect. 10 NC – No Connect. 11 BTS I Bus Type Select. 12 LIUC I Line Interface Connect. 13 8XCLK O Eight Times Clock. 14 TEST I Test. 15 NC – No Connect. 16 RTIP I Receive Analog Tip Input. 17 RRING I Receive Analog Ring Input. 18 RVDD – Receive Analog Positive Supply. 19 RVSS – Receive Analog Signal Ground. 20 RVSS – Receive Analog Signal Ground. 21 MCLK I Master Clock Input.
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DS2154 PIN SYMBOL TYPE DESCRIPTION 44 DVDD – Digital Positive Supply. 45 DVSS – Digital Signal Ground. 46 TCLK I Transmit Clock. 47 TSER I Transmit Serial Data. 48 TSIG I Transmit Signaling Input. 49 TESO O Transmit Elastic Store Output. 50 TDATA I Transmit Data. 51 TSYSCLK I Transmit System Clock. 52 TSSYNC I Transmit System Sync. 53 TCHCLK O Transmit Channel Clock. 54 NC – No Connect. Bus Operation.
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DS2154 PIN SYMBOL TYPE DESCRIPTION 79 RLCLK O Receive Link Clock. 80 DVSS – Digital SIgnal Ground. 81 DVDD – Digital Positive Supply. 82 RCLK O Receive Clock. 83 DVDD – Digital Positive Supply. 84 DVSS – Digital Signal Ground. 85 RDATA O Receive Data. 86 RPOSI I Receive Positive Data Input. 87 RNEGI I Receive Negative Data Input. 88 RCLKI I Receive Clock Input. 89 RCLKO O Receive Clock Output. 90 RNEGO O Receive Negative Data Output.
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DS2154 enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384K bps (H0), 768K bps, 1920K bps (H12) or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for external per–channel loopback, and for per–channel conditioning. See Section 9 for details. Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
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DS2154 Receive Channel Clock [RCHCLK]. 256 KHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data. Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low during any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
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DS2154 Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high. Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
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DS2154 Receive Analog Positive Supply [RVDD]. 5.0 volts ± 5%. Should be tied to the DVDD and TVDD pins. Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins. Transmit Analog Positive Supply [TVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and DVDD pins. Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins. Digital Signal Ground [DVSS]. 0.0 volts. Should be tied to the RVSS and TVSS pins.
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DS2154 ADDRESS R/W REGISTER NAME 1A R/W Common Control 2. REGISTER ABBREVIATION CCR2 1B R/W Common Control 3. CCR3 1C R/W Transmit Sa Bit Control. TSaCR 1D R/W Not present. 1E R Synchronizer Status. 1F R Receive Non–Align Frame. 20 R/W Transmit Align Frame. 21 R/W Transmit Non–Align Frame. 22 R/W Transmit Channel Blocking 1. TCBR1 23 R/W Transmit Channel Blocking 2. TCBR2 24 R/W Transmit Channel Blocking 3. TCBR3 25 R/W Transmit Channel Blocking 4.
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DS2154 ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION 3B R Receive Signaling 12. RS12 3C R Receive Signaling 13. RS13 3D R Receive Signaling 14. RS14 3E R Receive Signaling 15. RS15 3F R Receive Signaling 16. RS16 40 R/W Transmit Signaling 1. TS1 41 R/W Transmit Signaling 2. TS2 42 R/W Transmit Signaling 3. TS3 43 R/W Transmit Signaling 4. TS4 44 R/W Transmit Signaling 5. TS5 45 R/W Transmit Signaling 6. TS6 46 R/W Transmit Signaling 7.
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DS2154 ADDRESS R/W 5C R Receive Sa5 Bits. RSa5 5D R Receive Sa6 Bits. RSa6 5E R Receive Sa7 Bits. RSa7 5F R Receive Sa8 Bits. RSa8 60 R/W Transmit Channel 1. TC1 61 R/W Transmit Channel 2. TC2 62 R/W Transmit Channel 3. TC3 63 R/W Transmit Channel 4. TC4 64 R/W Transmit Channel 5. TC5 65 R/W Transmit Channel 6. TC6 66 R/W Transmit Channel 7. TC7 67 R/W Transmit Channel 8. TC8 68 R/W Transmit Channel 9. TC9 69 R/W Transmit Channel 10.
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DS2154 ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION 7D R/W Transmit Channel 30. TC30 7E R/W Transmit Channel 31. TC31 7F R/W Transmit Channel 32. TC32 80 R/W Receive Channel 1. RC1 81 R/W Receive Channel 2. RC2 82 R/W Receive Channel 3. RC3 83 R/W Receive Channel 4. RC4 84 R/W Receive Channel 5. RC5 85 R/W Receive Channel 6. RC6 86 R/W Receive Channel 7. RC7 87 R/W Receive Channel 8. RC8 88 R/W Receive Channel 9. RC9 89 R/W Receive Channel 10.
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DS2154 ADDRESS R/W REGISTER NAME 9E R/W Receive Channel 31. REGISTER ABBREVIATION RC31 9F R/W Receive Channel 32. RC32 A0 R/W Transmit Channel Control 1. TCC1 A1 R/W Transmit Channel Control 2. TCC2 A2 R/W Transmit Channel Control 3. TCC3 A3 R/W Transmit Channel Control 4. TCC4 A4 R/W Receive Channel Control 1. RCC1 A5 R/W Receive Channel Control 2. RCC2 A6 R/W Receive Channel Control 3. RCC3 A7 R/W Receive Channel Control 4. RCC4 A8 R/W Common Control 4.
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DS2154 IDR: DEVICE IDENTIFICATION REGISTER (Address= 0F Hex) (MSB) T1E1 (LSB) 0 0 0 ID3 ID2 ID1 ID0 SYMBOL POSITION NAME AND DESCRIPTION T1E1 IDR.7 T1 or E1 Chip Determination Bit. 0=T1 chip 1=E1 chip ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. ID2 IDR.1 Chip Revision Bit 2. ID1 IDR.2 Chip Revision Bit 1. ID0 IDR.0 Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
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DS2154 SYNC/RESYNC CRITERIA Table 3–1 FRAME OR MULTIFRAME LEVEL FAS SYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 RESYNC CRITERIA ITU SPEC. Three consecutive incorrect FAS received G.706 4.1.1 4.1.2 Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non–FAS received CRC4 Two valid MF alignment words found within 8 ms 915 or more CRC4 code words out of 1000 received in error G.706 4.2 and 4.3.
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DS2154 TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex) (MSB) ODF (LSB) TFPT T16S TUA1 TSiS TSA1 TSM TSIO SYMBOL POSITION NAME AND DESCRIPTION ODF TCR1.7 Output Data Format. 0=bipolar data at TPOSO and TNEGO 1=NRZ data at TPOSO; TNEGO=0 TFPT TCR1.6 Transmit Timeslot 0 Pass Through. 0=FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1=FAS bits/Sa bits/Remote Alarm sourced from TSER T16S TCR1.5 Transmit Timeslot 16 Data Select.
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DS2154 TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex) (MSB) Sa8S (LSB) Sa7S Sa6S Sa5S Sa4S ODM AEBE PF SYMBOL POSITION NAME AND DESCRIPTION Sa8S TCR2.7 Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See Section 13 for timing details. Sa7S TCR2.6 Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. See Section 13 for timing details. Sa6S TCR2.5 Sa6 Bit Select.
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DS2154 RHDB3 CCR1.2 Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled RG802 CCR1.1 Receive G.802 Enable. See Section 13 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26 RCRC4 CCR1.0 Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled FRAMER LOOPBACK When CCR1.7 is set to a one, the DS2154 will enter a Framer LoopBack (FLB) mode. See Figure 1–1 for more details. This loopback is useful in testing and debugging applications.
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DS2154 RFE CCR2.0 Receive Freeze Enable. See Section 7–2 for details. 0=no freezing of receive signaling data will occur 1=allow freezing of receive signaling data at RSIG (and RSER if CCR3.3=1). AUTOMATIC ALARM GENERATION When either CCR2.4 or CCR2.5 is set to one, the DS2154 monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception, or loss of receive carrier (or signal).
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DS2154 RCLA CCR3.0 Receive Carrier Loss (RCL) Alternate Criteria. 0=RCL declared upon 255 consecutive zeros (125 us) 1=RCL declared upon 2048 consecutive zeros (1 ms) POWER–UP SEQUENCE On power–up, after the supplies are stable, the DS2154 should be configured for operation by writing to all of the internal registers (this includes the Test Registers) since the contents of the internal registers cannot be predicted on power–up. Next, the LIRST (CCR5.
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DS2154 CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex) (MSB) LIRST (LSB) – – RCM4 RCM3 RCM2 RCM1 RCM0 SYMBOL POSITION NAME AND DESCRIPTION LIRST CCR5.7 Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power–up. Must be cleared and set again for a subsequent reset. – CCR5.6 Not Assigned. Should be set to zero when written – CCR5.
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DS2154 caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). The alarm caused interrupts will force the INT pin low whenever the alarm changes state (i.e. the alarm goes active or inactive according to the set/clear criteria in Table 4–1). The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present.
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DS2154 FASSA SSR.2 FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word. CRC4 SYNC COUNTER The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out.
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DS2154 ALARM CRITERIA Table 4–1 ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RSA1 (receive signaling all ones) over 16 consecutive frames (one full MF) timeslot 16 contains less than three zeros over 16 consecutive frames (one full MF) timeslot 16 contains three or more zeros G.732 4.2 RSA0 (receive signaling all zeros) over 16 consecutive frames (one full MF) timeslot 16 contains all zeros over 16 consecutive frames (one full MF) timeslot 16 contains at least a single one G.732 5.
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DS2154 IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex) (MSB) RSA1 (LSB) RDMA RSA0 RSLIP RUA1 RRA RCL SYMBOL POSITION RSA1 IMR1.7 Receive Signaling All Ones / Signaling Change. 0=interrupt masked 1=interrupt enabled RDMA IMR1.6 Receive Distant MF Alarm. 0=interrupt masked 1=interrupt enabled RSA0 IMR1.5 Receive Signaling All Zeros / Signaling Change. 0=interrupt masked 1=interrupt enabled RSLIP IMR1.4 Receive Elastic Store Slip Occurrence.
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DS2154 5.0 SEC IMR2.4 One Second Timer. 0=interrupt masked 1=interrupt enabled TAF IMR2.3 Transmit Align Frame. 0=interrupt masked 1=interrupt enabled LOTC IMR2.2 Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled RCMF IMR2.1 Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled TSLIP IMR2.0 Transmit Side Elastic Store Slip Occurrence.
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DS2154 5.2 CRC4 Error Counter CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4).
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DS2154 5.4 FAS Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is disabled during loss of frame synchronization conditions, it is not disabled during loss of synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one second period is 4000, this counter cannot saturate.
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DS2154 TCM3 CCR4.3 Transmit Channel Monitor Bit 3. TCM2 CCR4.2 Transmit Channel Monitor Bit 2. TCM1 CCR4.1 Transmit Channel Monitor Bit 1. TCM0 CCR4.0 Transmit Channel Monitor Bit 0. LSB of the channel decode that determines which transmit DS0 channel data will appear in the TDS0M register. TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex) (MSB) (LSB) B1 B2 B3 B4 B5 B6 B7 B8 SYMBOL POSITION NAME AND DESCRIPTION B1 TDS0M.7 Transmit DS0 Channel Bit 8.
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DS2154 RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=AB Hex) (MSB) 7.0 (LSB) B1 B2 B3 B4 SYMBOL POSITION NAME AND DESCRIPTION B1 RDS0M.7 Receive DS0 Channel Bit 8. MSB of the DS0 channel (first bit to be received). B2 RDS0M.6 Receive DS0 Channel Bit 7. B3 RDS0M.5 Receive DS0 Channel Bit 6. B4 RDS0M.4 Receive DS0 Channel Bit 5. B5 RDS0M.3 Receive DS0 Channel Bit 4. B6 RDS0M.2 Receive DS0 Channel Bit 3. B7 RDS0M.1 Receive DS0 Channel Bit 2. B8 RDS0M.
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DS2154 RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex) (MSB) (LSB) 0 0 0 0 X Y X X RS1 (30) A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) RS2 (31) A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) RS3 (32) A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18) RS4 (33) A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19) RS5 (34) A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20) RS6 (35) A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21) RS7 (36) A(7) B(7) C(7) D(
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DS2154 TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex) (MSB) (LSB) 0 0 0 0 X Y X X TS1 (40) A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) TS2 (41) A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) TS3 (42) A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18) TS4 (43) A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19) TS5 (44) A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20) TS6 (45) A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21) TS7 (46) A(7) B(7) C(7) D
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DS2154 TCBRs=0). See the Transmit Data Flow diagram in Section 13 for more details. 7.2 7.2.1 HARDWARE BASED SIGNALING Receive Side In the receive side of the hardware based signaling, there are two operating modes for the signaling buffer; signaling extraction and signaling re–insertion.
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DS2154 TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1 (MSB) (LSB) CH20 CH4 CH19 CH3 CH18 CH2 CH17* CH1* TCBR1(22) CH24 CH8 CH23 CH7 CH22 CH6 CH21 CH5 TCBR2(23) CH28 CH12 CH27 CH11 CH26 CH10 CH25 CH9 TCBR3(24) CH32 CH16 CH31 CH15 CH30 CH14 CH29 CH13 TCBR4(25) *=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits.
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DS2154 TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex) [Also used for Per–Channel Loopback] (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1 (26) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2 (27) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3 (28) CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TIR4 (29) SYMBOL POSITION CH32 TIR4.7 CH1 TIR1.0 NAME AND DESCRIPTION Transmit Idle Registers.
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DS2154 TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER (Address=A0 to A3 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCC1 (A0) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TCC2 (A1) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCC3 (A2) CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TCC4 (A3) 8.2 SYMBOL POSITION NAME AND DESCRIPTION CH1 TCC1.
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DS2154 9.0 CLOCK BLOCKING REGISTERS The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
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DS2154 TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1 (MSB) (LSB) CH20 CH4 CH19 CH3 CH18 CH2 CH17* CH1* TCBR1(22) CH24 CH8 CH23 CH7 CH22 CH6 CH21 CH5 TCBR2(23) CH28 CH12 CH27 CH11 CH26 CH10 CH25 CH9 TCBR3(24) CH32 CH16 CH31 CH15 CH30 CH14 CH29 CH13 TCBR4(25) *=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits. 10.
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DS2154 11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS2154 provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in Section 11.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is discussed in Section 11.2 The third method which is covered in Section 11.
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DS2154 RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex) (MSB) (LSB) Si 1 A Sa4 Sa5 Sa6 SYMBOL POSITION Si RNAF.7 International Bit. 1 RNAF.6 Frame Non–Alignment Signal Bit. A RNAF.5 Remote Alarm. Sa4 RNAF.4 Additional Bit 4. Sa5 RNAF.3 Additional Bit 5. Sa6 RNAF.2 Additional Bit 6. Sa7 RNAF.1 Additional Bit 7. Sa8 RNAF.0 Additional Bit 8.
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DS2154 A TNAF.5 Remote Alarm (used to transmit the alarm). Sa4 TNAF.4 Additional Bit 4. Sa5 TNAF.3 Additional Bit 5. Sa6 TNAF.2 Additional Bit 6. Sa7 TNAF.1 Additional Bit 7. Sa8 TNAF.0 Additional Bit 8. 11.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received.
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DS2154 REGISTER NAME ADDRESS (HEX) RSiAF 58 The eight Si bits in the align frame RSiNAF 59 The eight Si bits in the non–align frame RRA 5A The eight reportings of the receive remote alarm (RA) RSa4 5B The eight Sa4 reported in each CRC4 multiframe RSa5 5C The eight Sa5 reported in each CRC4 multiframe RSa6 5D The eight Sa6 reported in each CRC4 multiframe RSa7 5E The eight Sa7 reported in each CRC4 multiframe RSa8 5F The eight Sa8 reported in each CRC4 multiframe TSiAF 50 The ei
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DS2154 Sa6 TSaCR.2 Additional Bit 6 Insertion Control Bit. 0=do not insert data from the TSa6 register into the transmit data stream 1=insert data from the TSa6 register into the transmit data stream Sa7 TSaCR.1 Additional Bit 7 Insertion Control Bit. 0=do not insert data from the TSa7 register into the transmit data stream 1=insert data from the TSa7 register into the transmit data stream Sa8 TSaCR.0 Additional Bit 8 Insertion Control Bit.
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DS2154 nal is present at RTIP and RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLKO will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry.
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DS2154 12.3 JITTER ATTENUATOR The DS2154 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128–bit mode is used in applications where large excursions of wander are expected. The 32–bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 12–4.
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DS2154 DS2154 JITTER TOLERANCE Figure 12–2 1K 100 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ DS2154 TOLERANCE UNIT INTERVALS (UIpp) 40 10 1.5 1 MINIMUM TOLERANCE LEVEL AS PER ITU G.823 0.1 10 20 1 0.2 100 1K 2.4K 10K 18K 100K FREQUENCY (Hz) DS2154 TRANSMIT WAVEFORM TEMPLATE Figure 12–3 1. 2 1.
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DS2154 DS2154 JITTER ATTENUATION Figure 12–4 ÊÊÊÊÊÊÊÊÊÊÊÊÊ ÊÊÊÊÊÊÊÊÊÊÊÊÊ ÊÊÊÊÊÊÊÊÊÊÊÊÊ ÊÊÊÊÊÊÊÊÊÊÊÊÊ ÊÊÊÊÊÊÊÊÊÊÊÊÊ 0 dB J I T T E R A T T E N U A T IO N ( d B ) ITU G.
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DS2154 13.0 TIMING DIAGRAMS/SYNC FLOWCHART/TRANSMIT DATA FLOW DIAGRAM RECEIVE SIDE TIMING Figure 13–1 FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 RSYNC1/ RFSYNC RSYNC2 RLCLK3 RLINK4 NOTES: 1. RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to pulse high during the Sa4 bit position. 4. RLINK will always output all five Sa bits as well as the rest of the receive data stream. 5.
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DS2154 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 13–3 RSYSCLK CHANNEL 23/31 CHANNEL 24/32 RSER1 LSB CHANNEL 1/2 MSB LSB F MSB RSYNC2/ RMSYNC RSYNC3 RCHCLK RCHBLK4 NOTES: 1. Data from the E1 Channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (Channel 2 from the E1 link is mapped to Channel 1 of the T1 link, etc.) and the F–bit position is added (forced to one). 2. RSYNC is in the output mode (RCR1.5=0). 3. RSYNC is in the input mode (RCR1.5=1). 4.
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DS2154 TRANSMIT SIDE TIMING Figure 13–5 FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 TSYNC1/ TFSYNC TSYNC2 TLCLK3 TLINK3 NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame.
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DS2154 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 13–7 TSYSCLK CHANNEL 23 CHANNEL 1 CHANNEL 24 TSER LSB MSB LSB MSB F–BIT TSSYNC TCHCLK TCHBLK1 NOTES: 1. TCHBLK is programmed to block Channel 23. 2. The F–bit position is ignored by the DS2154. TRANSMIT SIDE 2.048 MHz (WITH ELASTIC STORE ENABLED) Figure 13–8 TSYSCLK CHANNEL 31 CHANNEL 32 TSER LSB CHANNEL 1 MSB LSB MSB TSSYNC CHANNEL 31 TSIG A B D TCHCLK TCHBLK1 NOTE: 1.
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DS2154 G.802 TIMING Figure 13–9 TIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 RSYNC/ TSYNC RCHCLK/ TCHCLK RCHBLK/ TCHBLK1 DETAIL RCLK/RSYSCLK TCLK/TSYSCLK TIMESLOT 25 RSER/TSER TIMESLOT 26 LSB MSB RCHCLK/TCHCLK RCHBLK/TCHCLK NOTE: 1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit 1 of timeslot 26.
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DS2154 DS2154 SYNCHRONIZATION FLOWCHART Figure 13–10 POWER UP RLOS=1 FAS SEARCH FASSA=1 RLOS=1 FAS SYNC CRITERIA MET FASSA=0 RESYNC IF RCR1.1=0 INCREMENT CRC4 SYNC COUNTER; CRC4SA=0 8 MS TIME OUT CRC4 SYNC CRITERIA MET; CRC4SA=0; RESET CRC4 SYNC COUNTER SET FASRC (RIR.1) CRC4 RESYNC CRITERIA MET (RIR.2) IF CAS IS ON (CCR1.3=0) 031197 56/69 FAS RESYNC CRITERIA MET CHECK FOR >=915 OUT OF 1000 CRC CRC WORD ERROS CAS RESYNC CRITERIA MET; SET CASRC (RIR.
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DS2154 DS2154 TRANSMIT DATA FLOW Figure 13–11 TSER & TDATA RSER (note 1) TLINK TC1 TO TC32 PER–CHANNEL CODE GENERATION (TCC1/2/3/4) TAF TNAF 1 0 TIMESLOT 0 PASS–THROUGH (TCR1.6) 1 0 Si BIT INSERTION CONTROL (TCR1.3) RECEIVE SIDE CRC4 ERROR DETECTOR CRC4 MULTIFRAME ALIGNMENT WORD GENERATION(CCR1.4) TSiAF TSiNAF 0 1 TRA E–BIT GENERATION (TCR2.1) 0 TIDR TSa4 to TSa8 0 1 1 TIR FUNCTION SELECT (CCR3.5) Sa BIT INSERTION CONTROL (TCR2.3 THRU TCR2.7) AUTO REMOTE ALARM GENERATION (CCR2.
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DS2154 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS2154L Operating Temperature for DS2154LN Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –40°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
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DS2154 AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX=1) (0°C to 70°C; VDD=5V ± 5% for DS2154L; –40°C to +85°C; VDD=5V ± 5% for DS2154LN) PARAMETER SYMBOL MIN tCYC 200 ns Pulse Width, DS low or RD high PWEL 100 ns Pulse Width, DS high or RD low PWEH 100 ns Input Rise/Fall times tR, tF R/W Hold Time tRWH 10 ns R/W Set Up time before DS high tRWS 50 ns CS Set Up time before DS, WR or RD active tCS 20 ns CS Hold time tCH 0 ns Read Data Hold time tDHR 10 Write Data Hold
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DS2154 (0°C to 70°C; VDD=5V ± 5% for DS2154L; –40°C to +85°C; VDD=5V ± 5% for DS2154LN) AC CHARACTERISTICS – RECEIVE SIDE PARAMETER SYMBOL RCLKO Period tLP RCLKO Pulse Width tLH tLL RCLKO Pulse Width tLH tCL RCLKI Period tCP RCLKI Pulse Width tCH tCL 75 75 RSYSCLK Period tSP tSP 122 122 RSYSCLK Pulse Width tSH tSL 50 50 RSYNC Set Up to RSYSCLK Falling tSU 20 RSYNC Pulse Width tPW 50 ns RPOSI/RNEGI Set Up to RCLKI Falling tSU 20 ns RPOSI/RNEGI Hold From RCLKI Falling tHD 20
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DS2154 14.0 A. C. AND D. C.
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DS2154 MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 14–3 PWASH AS PWEH DS tASD tASED PWEL tCYC tRWS tRWH R/W tASL tDDR tDHR AD0-AD7 (READ) tAHL tCH tCS CS tASL AD0-AD7 (WRITE) tDSW tDHW tAHL RECEIVE SIDE AC TIMING Figure 14–4 RCLK tD1 MSB OF CHANNEL 1 RSER/RDATA/RSIG tD2 RCHCLK tD2 RCHBLK tD2 RFSYNC/RMSYNC tD2 RSYNC1 tD2 RLCLK2 tD1 RLINK Sa4 TO Sa8 BIT POSITION NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2.
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DS2154 (0°C to 70°C; VDD=5V ± 5% for DS2154L; –40°C to +85°C; VDD=5V ± 5% for DS2154LN) AC CHARACTERISTICS – TRANSMIT SIDE PARAMETER SYMBOL MIN TYP MAX TCLK Period tCP TCLK Pulse Width tCH tCL TCLKI Period tLP TCLKI Pulse Width tLH tLL 75 75 TSYSCLK Period tSP tSP 122 122 TSYSCLK Pulse Width tSH tSL 50 50 TSYNC or TSSYNC Set Up to TCLK or TSYSCLK falling tSU 20 TSYNC or TSSYNC Pulse Width tPW 50 ns TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Set Up to TCLK, TSYSCLK, TCLKI Falling tS
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DS2154 RECEIVE SYSTEM SIDE AC TIMING Figure 14–5 tR tSL tF tSH RSYSCLK tSP tD3 MSB OF CHANNEL 1 RSER/RSIG tD4 RCHCLK tD4 RCHBLK tD4 RMSYNC tD4 RSYNC1 tPW tSU RSYNC2 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1).
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DS2154 TRANSMIT SIDE AC TIMING Figure 14–7 tCP tR tCL tF tCH TCLK tD1 TESO tSU TSER/TSIG/ TDATA tHD tD2 TCHCLK tD2 TCHBLK tD2 TSYNC1 tPW tSU TSYNC2 tD2 TLCLK5 tHD TLINK tSU NOTES: 1. TSYNC is in the output mode (TCR1.0=1). 2. TSYNC is in the input mode (TCR1.0=0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5.
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DS2154 TRANSMIT SYSTEM SIDE AC TIMING Figure 14–8 tSP tR tSL tF tSH TSYSCLK tSU TSER tHD tD3 TCHCLK tD3 TCHBLK tPW tSU TSSYNC NOTES: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
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DS2154 AC CHARACTERISTICS – NON–MULTIPLEXED PARALLEL PORT (MUX=0 ) (0°C to 70°C; VDD=5V ± 5% for DS2154T; –40°C to +85°C; VDD=5V ± 5% for DS2154TN) PARAMETER SYMBOL MIN Set Up Time for A0 to A7 Valid to CS Active t1 0 TYP MAX UNITS ns Set Up Time for CS Active to either RD, WR, or DS Active t2 0 ns Delay Time from either RD or DS Active to Data Valid t3 Hold Time from either RD, WR, or DS Inactive to CS Inactive t4 0 Hold Time from CS Inactive to Data Bus 3–state t5 5 Wait Time from ei
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DS2154 INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 14–11 t9 10 ns min. A0 TO A7 ADDRESS VALID D0 TO D7 t7 RD t1 t8 10 ns 10 ns min. min. 0 ns min. CS 0 ns min. t2 t6 t4 0 ns min. 75 ns min. WR MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 14–12 A0 TO A7 ADDRESS VALID D0 TO D7 DATA VALID 5 ns min. /20 ns max. t5 R/W t1 0 ns min. CS 0 ns min. t2 t3 t4 0 ns min. 75 ns max. DS MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 14–13 t9 10 ns min.
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DS2154 DS2154 100–PIN LQFP PKG 100–PIN DIM MIN MAX A – 1.60 A1 0.05 – A2 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 15.80 16.20 D1 E 14.00 BSC 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.