User Manual

DS2153Q
022697 47/48
TRANSMIT SIDE AC TIMING Figure 14–5
TCLK
TSER
4
TCHCLK
TCHBLK
TSYNC
1
TSYNC
2
TLCLK
3
TLINK
3
t
R
t
F
t
CL
t
P
t
CH
t
SU
t
HD
t
D1
t
D2
t
D3
t
PW
t
SU
t
D4
t
HD
t
SU
MSBLSB
NOTES:
1. TSYNC is in the output mode (TCR1.0=1).
2. TSYNC is in the input mode (TCR1.0=0).
3. No timing relationship between TSYNC and TLCLK/TLINK is implied.
4. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.