User Manual

DS2153Q
022697 36/48
TRANSMIT SIDE BOUNDARY TIMING Figure 13–6
TCLK
TSER
TSYNC
1
TSYNC
2
TCHCLK
CHANNEL 2CHANNEL 1
TCHBLK
3
TLCLK
4
TLINK
4
Don’t Care
LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB MSBLSB
Don’t Care
TLCLK
5
TLINK
5
Don’t CareDon’t Care
NOTES:
1. TSYNC is in the input mode (TCR1.0=0).
2. TSYNC is in the output mode (TCR1.0=1).
3. TCHBLK is programmed to block channel 2.
4. TLINK is programmed to source the Sa4 bits.
5. TLINK is programmed to source the Sa7 and Sa8 bits.
6. Shown is a non–align frame boundary.
7. See Figures 13.3 and 13.4 for details on timing with the transmit side elastic store enabled.