User Manual

DS2153Q
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RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) (LSB)
TESF TESE JALT RESF RESE CRCRC FASRC CASRC
SYMBOL POSITION NAME AND DESCRIPTION
TESF RIR.7 Transmit Elastic Store Full. Set when the elastic store fills and a frame is
deleted.
TESE RIR.6 Transmit Elastic Store Empty. Set when the elastic store empties and a
frame is repeated.
JALT RIR.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to
within 4–bits of it’s limit; useful for debugging jitter attenuation operation.
RESF RIR.4 Elastic Store Full. Set when the elastic store buffer fills and a frame is
deleted.
RESE RIR.3 Elastic Store Empty. Set when the elastic store buffer empties and a
frame is repeated.
CRCRC RIR.2 CRC Resync Criteria Met. Set when 915/1000 code words are received in
error.
FASRC RIR.1 FAS Resync Criteria Met. Set when three consecutive FAS words are
received in error.
CASRC RIR.0 CAS Resync Criteria Met. Set when two consecutive CAS MF alignment
words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) (LSB)
CSC5
CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA
SYMBOL POSITION NAME AND DESCRIPTION
CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CSC4 SSR.6 CRC4 Sync Counter Bit 4.
CSC3 SSR.5 CRC4 Sync Counter Bit 3.
CSC2 SSR.4 CRC4 Sync Counter Bit 2.
CSC0 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB bit is
not accessible. This bit will toggle each time the CRC4 MF search times out
at 8 ms.
FASSA SSR.2 FAS Sync Active. Set while the synchronizer is searching for alignment at
the FAS level.
CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching for the CAS
MF alignment word.
CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching for the
CRC4 MF alignment word.