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DS2152
031897 62/79
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15–4
RSYSCLK
CHANNEL 24 CHANNEL 1CHANNEL 23
LSB MSB
RSER
RSYNC
1
RMSYNC
RSYNC
2
RSIG
RCHCLK
RCHBLK
3
LSB MSBF
CHANNEL 24 CHANNEL 1CHANNEL 23
A B C/A D/B A B C/A D/B
A
NOTES:
1. RSYNC is in the output mode (RCR2.3=0).
2. RSYNC is in the input mode (RCR2.3=1).
3. RCHBLK is programmed to block channel 24.
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 15–5
RSYSCLK
CHANNEL 32 CHANNEL 1CHANNEL 31
LSB MSB
CHANNEL 31 CHANNEL 1
CHANNEL 32
RSER
1
RSYNC
2
RMSYNC
RSYNC
3
RSIG
RCHCLK
RCHBLK
4
LSB
F
5
A B C/A D/B A B C/A D/B
NOTES:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one.
2. RSYNC is in the output mode (RCR2.3=0).
3. RSYNC is in the input mode (RCR2.3=1).
4. RCHBLK is forced to one in the same channels as RSER (see Note 1).
5. The F–Bit position is passed through the receive side elastic store.
6. RCHCLK does not transition high in the channels in which the RSER data is forced to one (see note 1).