Owner's manual

DS2152
031897 47/79
RPS FDLS.5 Receive Packet Start. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RPRM register for
details.
RHALF FDLS.4 Receive FIFO Half Full. Set when the receive 16–byte FIFO fills beyond
the half way point. The setting of this bit prompts the user to read the RPRM
register for details.
RNE FDLS.3 Receive FIFO Not Empty. Set when the receive 16–byte FIFO has at least
one byte available for a read. The setting of this bit prompts the user to read
the RPRM register for details.
THALF FDLS.2 Transmit FIFO Half Empty. Set when the transmit 16–byte FIFO empties
beyond the half way point. The setting of this bit prompts the user to read
the TPRM register for details.
TNF FDLS.1 Transmit FIFO Not Full. Set when the transmit 16–byte FIFO has at least
one byte available. The setting of this bit prompts the user to read the
TPRM register for details.
TMEND FDLS.0 Transmit Message End. Set when the transmit HDLC controller has fin-
ished sending a message. The setting of this bit prompts the user to read
the TPRM register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
FIMR: FDL INTERRUPT MASK REGISTER (Address=02 Hex)
(MSB) (LSB)
RBOC
RPE RPS RHALF RNE THALF TNF TMEND
SYMBOL POSITION NAME AND DESCRIPTION
RBOC FIMR.7 Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
RPE FIMR.6 Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
RPS FIMR.5 Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
RHALF FIMR.4 Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
RNE FIMR.3 Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
THALF FIMR.2 Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled