Owner's manual

DS2152
031897 42/79
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers
(RCBR1/RCBR2/RCBR3) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3) control
the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user programmable
outputs that can be forced either high or low during indi-
vidual channels. These outputs can be used to block
clocks to a USART or LAPD controller in Fractional T1
or ISDN–PRI applications. When the appropriate bits
are set to a one, the RCHBLK and TCHCLK pins will be
held high during the entire corresponding channel time.
See the timing in Section 15 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 RCBR3.7 Receive Channel Blocking Registers.
0=force the RCHBLK pin to remain low during this channel time
CH1 RCBR1.0 1=force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB) (LSB)
CH8
CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 TCBR3.7 Transmit Channel Blocking Registers.
0=force the TCHBLK pin to remain low during this channel time
CH1 TCBR1.0 1=force the TCHBLK pin high during this channel time
10.0 ELASTIC STORES OPERATION
The DS2152 contains dual two–frame (386 bits) elastic
stores, one for the receive direction, and one for the
transmit direction. These elastic stores have two main
purposes. First, they can be used to rate convert the T1
data stream to 2.048 Mbps (or a multiple of 2.048 Mbps)
which is the E1 rate. Secondly, they can be used to
absorb the differences in frequency and phase between
the T1 data stream and an asynchronous (i.e., not fre-
quency locked) backplane clock (which can be
1.544 MHz or 2.048 MHz). The backplane clock can
burst at rates up to 8.192 MHz. Both elastic stores con-
tain full controlled slip capability which is necessary for
this second purpose. The receive side elastic store can
be enabled via CCR1.2 and the transmit side elastic
store is enabled via CCR1.7. The elastic stores can be
forced to a known depth via the Elastic Store Reset bit
(CCR3.6). Toggling the CCR3.6 bit forces the read and
write pointers into opposite frames. Both elastic stores
within the DS2152 are fully independent and no restric-
tions apply to the sourcing of the various clocks that are
applied to them. The transmit side elastic store can be
enabled whether the receive elastic store is enabled or
disabled and vice versa. Also, each elastic store can
interface to either a 1.544 MHz or 2.048 MHz backplane
without regard to the backplane rate the other elastic
store is interfacing.
RCBR1 (6C)
RCBR2 (6D)
RCBR3 (6E)
RCBR1 (32)
RCBR2 (33)
RCBR3 (34)