Owner's manual

DS2152
031897 15/79
ADDRESS REGISTER ABBREVIATIONREGISTER NAMER/W
76 R/W Transmit Signaling 7 TS7
77 R/W Transmit Signaling 8 TS8
78 R/W Transmit Signaling 9 TS9
79 R/W Transmit Signaling 10 TS10
7A R/W Transmit Signaling 11 TS11
7B R/W Transmit Signaling 12 TS12
7C R/W Line Interface Control LICR
7D R/W Test 1 TEST1 (set to 00h)
7E R/W Transmit FDL Register TFDL
7F R/W Interrupt Mask Register 1 IMR1
80 R/W Receive Channel 1 RC1
81 R/W Receive Channel 2 RC2
82 R/W Receive Channel 3 RC3
83 R/W Receive Channel 4 RC4
84 R/W Receive Channel 5 RC5
85 R/W Receive Channel 6 RC6
86 R/W Receive Channel 7 RC7
87 R/W Receive Channel 8 RC8
88 R/W Receive Channel 9 RC9
89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15
8F R/W Receive Channel 16 RC16
NOTES:
1. Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on pow-
er–up initialization to insure proper operation.
2. Register banks 9xh, Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
2.0 PARALLEL PORT
The DS2152 is controlled via either a non–multiplexed
(MUX = 0) or a multiplexed (MUX = 1) bus by an external
microcontroller or microprocessor. The DS2152 can
operate with either Intel or Motorola bus timing configu-
rations. If the BTS pin is tied low, Intel timing will be
selected; if tied high, Motorola timing will be selected.
All Motorola bus signals are listed in parenthesis (). See
the timing diagrams in the A.C. Electrical Characteris-
tics in Section 16 for more details.