Owner manual

DS2151Q
022697 45/46
TRANSMIT SIDE AC TIMING
TCLK
TSER
3
TCHCLK
TCHBLK
TSYNC
1
TSYNC
2
TLCLK
TLINK
t
R
t
F
t
CL
t
P
t
CH
t
SU
t
HD
t
D1
t
D2
t
D3
t
PW
t
SU
t
D4
t
HD
t
SU
F–BIT
NOTES:
1. TSYNC is in the output mode (TCR2.2=1).
2. TSYNC is in the input mode (TCR2.2=0).
3. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.