Owner manual

DS2151Q
022697 43/46
RECEIVE SIDE AC TIMING
RCLK
RSER
RCHCLK
RCHBLK
RSYNC
1
RSYNC
2
RLCLK
RLINK
t
D5
t
CL
t
CH
t
CP
t
SU
t
D4
t
PW
t
D3
t
D2
t
DD
F–BIT OR MSB
SYSCLK
t
R
t
F
t
SL
t
SH
t
SP
OF CHANNEL 1
t
D1
NOTES:
1. RSYNC is in the output mode (RCR2.3=0).
2. RSYNC is in the input mode (RCR2.3=1).
3. RLCLK and RLINK only have a timing relationship to RCLK.
4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.