DS21455/DS21458 Quad T1/E1/J1 Transceivers
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Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0)
Figure 38-5. Intel Bus Write Timing (BTS = 0 / MUX = 0)
Address Valid
Data Valid
A0 to A9
D0 to D7
WR
CS
RD*
t1
t2 t3 t4
t5
Address ValidA0 to A9
D0 to D7
RD
CS
WR
t1
t2 t6 t4
t7 t8
