Owner's manual

DS21455/DS21458 Quad T1/E1/J1 Transceivers
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31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER
The DS21455/DS21458 contain an on-chip clock synthesizer that generates a user-selectable clock
referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate
low-jitter clocks. Common applications include generation of port and backplane system clocks.
Register Name:
CCR2
Register Description:
Common Control Register 2
Register Address:
71h
Bit # 7 6 5 4 3 2 1 0
Name — — — — — BPCS1 BPCS0 BPEN
Default 0 0 0 0 0 0 0 0
Bit 0/Backplane Clock Enable (BPEN).
0 = disable BPCLK pin (Pin held at logic 0)
1 = enable BPCLK pin
Bits 1 to 2/Backplane Clock Selects (BPCS0, BPCS1).
BPCS1 BPCS0 BPCLK FREQUENCY (MHz)
0 0 16.384
0 1 8.192
1 0 4.096
1 1 2.048
Bit 3/Unused, must be set to zero for proper operation.
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Unused, must be set to zero for proper operation.