Manual

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DS2143/DS2143Q

031397 7/40

ADDRESS

A7 to A0

HEX R/W REGISTER NAME

00111011 3B R Receive Signaling

00111100 3C R Receive Signaling

00111101 3D R Receive Signaling

00111110 3E R Receive Signaling

00111111 3F R Receive Signaling

01000000 40 R/W Transmit Signaling

01000001 41 R/W Transmit Signaling

01000010 42 R/W Transmit Signaling

01000011 43 R/W Transmit Signaling

01000100 44 R/W Transmit Signaling

01000101 45 R/W Transmit Signaling

01000110 46 R/W Transmit Signaling

01000111 47 R/W Transmit Signaling

01001000 48 R/W Transmit Signaling

01001001 49 R/W Transmit Signaling

01001010 4A R/W Transmit Signaling

01001011 4B R/W Transmit Signaling

01001100 4C R/W Transmit Signaling

01001101 4D R/W Transmit Signaling

01001110 4E R/W Transmit Signaling

01001111 4F R/W Transmit Signaling

2.0 PARALLEL PORT

The DS2143 is controlled via a mutliplexed bidirectional

address/data bus by an external microcontroller or

microprocessor. The DS2143 can operate with either

Intel or Motorola bus timing configurations. If the BTS

pin is tied low, Intel timing will be selected; if tied high,

Motorola timing will be selected. All Motorola bus sig-

nals are listed in parenthesis (). See the timing dia-

grams in the AC Electrical Characteristics for more

details. The mutliplexed bus on the DS2143 saves pins

because the address information and data information

share the same signal paths. The addresses are pres-

ented to the pins in the first portion of the bus cycle and

data will be transferred on the pins during second por-

tion of the bus cycle. Addresses must be valid prior to

the falling edge of ALE(AS), at which time the DS2143

latches the address from the AD0 to AD7 pins. Valid

write data must be present and held stable during the

later portion of the DS or WR

pulses. In a read cycle, the

DS2143 outputs a byte of data during the latter portion of

the DS or RD pulses. The read cycle is terminated and

the bus returns to a high impedance state as RD transi-

tions high in Intel timing or as DS transitions low in Moto-

rola timing.

3.0 CONTROL AND TEST REGISTERS

The operation of the DS2143 is configured via a set of

five registers. Typically, the control registers are only

accessed when the system is first powered up. Once

the DS2143 has been initialized, the control registers

will only need to be accessed when there is a change in

the system configuration. There are two Receive Con-

trol Registers (RCR1 and RCR2), two Transmit Control

Registers (TCR1 and TCR2), and a Common Control

in this section.

The Test Register at address 15 hex is used by the fac-

tory in testing the DS2143. On power–up, the Test Reg-

ister should be set to 00 hex in order for the DS2143 to

operate properly.