Manual

DS2143/DS2143Q
031397 28/40
TRANSMIT SIDE BOUNDARY TIMING
TCLK
TSER
1
TPOS,
TNEG
1
TSYNC
2
TSYNC
3
TCHCLK
CHANNEL 2CHANNEL 1
CHANNEL 2CHANNEL 1CHANNEL 32
TCHBLK
4
TLCLK
5
TLINK
5
Don’t Care
LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB MSBLSB
MSB LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB
Don’t Care
TLCLK
6
TLINK
6
Don’t CareDon’t Care
NOTES:
1. There is a 5 TCLK delay from TSER to TPOS, and TNEG.
2. TSYNC is in the input mode (TCR1.0=0).
3. TSYNC is in the output mode (TCR1.0=1).
4. TCHBLK is programmed to block channel 2.
5. TLINK is programmed to source the Sa4 bits.
6. TLINK is programmed to source the Sa7 and Sa8 bits.
7. Shown is a non–align frame boundary.