Manual

DS2143/DS2143Q
031397 2/40
1.0 INTRODUCTION
The DS2143 E1 Controller has four main sections: the
receive side, the transmit side, the line interface control-
ler, and the parallel control port. See the Block Diagram.
On the receive side, the device will clock in the serial E1
stream via the RPOS and RNEG pins. The synchro-
nizer will locate the frame and multiframe patterns and
establish their respective positions. This information
will be used by the rest of the receive side circuitry.
The DS2143 is an “off–line” framer, which means that all
of the E1 serial stream that goes into the device, will
come out of it, unchanged. Once the E1 data has been
framed to, the signaling data can be extracted. The
two–frame elastic store can either be enabled or
bypassed.
The transmit side clocks in the unframed E1 stream at
TSER and adds in the framing pattern and the signaling.
The line Interface control port will update line interface
devices that contain a serial port. The parallel control
port contains a multiplexed address and data structure
which can be connected to either a microcontroller or
microprocessor.
Reader’s Note:
This data sheet assumes a particular nomenclature of
the E1 operating environment. There are 32 eight–bit
timeslots in an E1 systems which are number 0 to 31.
Timeslot 0 is transmitted first and received first. These
32 timeslots are also referred to as channels with a num-
bering scheme of 1 to 32. Timeslot 0 is identical to chan-
nel 1, timeslot 1 is identical to channel 2, and so on.
Each timeslot (or channel) is made up of eight bits which
are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is trans-
mitted last. Throughout this data sheet, the following
abbreviations will be used:
FAS Frame Alignment Signal
CRC4 Cyclical Redundancy Check
CAS Channel Associated Signaling
CCS Common Channel Signaling
MF Multiframe
Sa Additional bits
Si International bits
E–bit CRC4 Error bits
DS2143 FEATURES
• Parallel control port
• Onboard two–frame elastic store
• CAS signaling bit extraction and insertion
• Fully independent transmit and receive sections
• Full alarm detection
• Full access to Si and Sa bits
• Loss of transmit clock detection
• HDB3 coder/decoder
• Full transmit transparency
• Large error counters
• Individual bit–by–bit Sa data link support circuitry
• Programmable output clocks
• Frame sync generation
• Local loopback capability
• Automatic CRC4 E–bit support
• Loss of receive clock detection
• G.802 E1 to T1 mapping support