Manual

DS2143/DS2143Q
031397 12/40
The SR1 and SR2 registers have the unique ability to
initiate a hardware interrupt via the INT1
and INT2 pins
respectively. Each of the alarms and events in the SR1
and SR2 can be either masked or unmasked from the
interrupt pins via the Interrupt Mask Register 1 (IMR1)
and Interrupt Mask Register 2 (IMR2) respectively.
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) (LSB)
–
– – ESF ESE – FASRC CASRC
SYMBOL POSITION NAME AND DESCRIPTION
– RIR.7 Not Assigned. Could be any value when read.
– RIR.6 Not Assigned. Could be any value when read.
– RIR.5 Not Assigned. Could be any value when read.
ESF RIR.4 Elastic Store Full. Set when the elastic store buffer fills and a frame is
deleted.
ESE RIR.3 Elastic Store Empty. Set when the elastic store buffer empties and a
frame is repeated.
– RIR.2 Not Assigned. Could be any value when read.
FASRC RIR.1 FAS Resync Criteria Met. Set when three consecutive FAS words are
received in error.
CASRC RIR.0 CAS Resync Criteria Met. Set when two consecutive CAS MF alignment
words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) (LSB)
CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA
SYMBOL POSITION NAME AND DESCRIPTION
CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CSC4 SSR.6 CRC4 Sync Counter Bit 4.
CSC3 SSR.5 CRC4 Sync Counter Bit 3.
CSC2 SSR.4 CRC4 Sync Counter Bit 2.
CSC1 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB is not
accessible.
FASSA SSR.2 FAS Sync Active. Set while the synchronizer is searching for alignment at
the FAS level.
CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching for the CAS
MF alignment word.
CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching for the
CRC4 MF alignment word.