DS2143/DS2143Q DS2143/DS2143Q E1 Controller FEATURES PIN ASSIGNMENT • E1/ISDN–PRI framing transceiver TCLK 1 40 VDD TSER 2 39 TSYNC TCHCLK 3 38 TLINK TPOS 4 37 TLCLK TNEG 5 36 INT1 AD0 6 35 INT2 AD1 7 AD3 8 9 34 33 RLOS/LOTC AD2 AD4 • Onboard Sa data link support circuitry AD5 • FEBE E–Bit Detection, Counting and Generation • Frames to CAS, CCS, and CRC4 formats • Parallel Control Port • Onboard two frame elastic store slip buffer • Extracts and inserts CAS signaling b
DS2143/DS2143Q 1.0 INTRODUCTION DS2143 FEATURES The DS2143 E1 Controller has four main sections: the receive side, the transmit side, the line interface controller, and the parallel control port. See the Block Diagram. On the receive side, the device will clock in the serial E1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and multiframe patterns and establish their respective positions. This information will be used by the rest of the receive side circuitry.
DS2143/DS2143Q DS2143 BLOCK DIAGRAM RLINK RLCLK RLOS RCHBLK RCHCLK E–BIT COUNT SIGNALING EXTRACTION ALARM DETECTION LOCAL LOOPBACK CRC4 ERROR COUNT RCLK RNEG BPV COUNTER RPOS SYNCHRONIZER HDB3 DECODER RECEIVE SIDE FRAMER TIMING CONTROL/ Sa EXTRACTION RSER ELASTIC STORE RSYNC TCLK Si BIT INSERTION FAS WORD INSERTION E–BIT INSERTION Sa BIT INSERTION SIGNALING INSERTION CRC4 GENERATION IDLE CODE INSERTION TNEG HDB3 ENCODE AIS GENERATION TRANSMIT SIDE FORMATTER TPOS TSER TSYNC TIM
DS2143/DS2143Q PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION 1 TCLK I Transmit Clock. 2.048 MHz primary clock. A clock must be applied at the TCLK pin for the parallel port to operate properly. 2 TSER I Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge of TCLK. 3 TCHCLK O Transmit Channel Clock. 256 KHz clock which pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel data. See Section 13 for timing details.
DS2143/DS2143Q PIN SYMBOL TYPE DESCRIPTION 30 LI_CLK O Serial Port Clock for the Line Interface. Connects directly to the SCLK input pin on the line interface. See Sections 12 and 13 for timing details. 31 LI_CS O Serial Port Chip Select for the Line Interface. Connects directly to the CS input pin on the line interface. See Sections 12 and 13 for timing details. 32 33 RCHBLK TCHBLK O Receive/Transmit Channel Block.
DS2143/DS2143Q DS2143 REGISTER MAP ADDRESS A7 to A0 HEX R/W 00000000 00 R 00000001 01 00000010 ADDRESS A7 to A0 HEX R/W REGISTER NAME Bipolar Violation Count Register 1. 00100011 23 R/W Transmit Channel Blocking Register 2. R Bipolar Violation Count Register 2. 00100100 24 R/W Transmit Channel Blocking Register 3. 02 R CRC4 Count Register 1. 00100101 25 R/W 00000011 03 R CRC4 Count Register 2. Transmit Channel Blocking Register 4. 00000100 04 R E–Bit Count Register 1.
DS2143/DS2143Q ADDRESS A7 to A0 HEX R/W REGISTER NAME 00111011 3B R Receive Signaling Register 12. 00111100 3C R Receive Signaling Register 13. 00111101 3D R Receive Signaling Register 14. 00111110 3E R Receive Signaling Register 15. 00111111 3F R Receive Signaling Register 16. 01000000 40 R/W Transmit Signaling Register 1. 01000001 41 R/W Transmit Signaling Register 2. 01000010 42 R/W Transmit Signaling Register 3. 01000011 43 R/W Transmit Signaling Register 4.
DS2143/DS2143Q RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex) (MSB) RSMF (LSB) RSM RSIO – – FRC SYNCE RESYNC SYMBOL POSITION NAME AND DESCRIPTION RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR1.6=1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries RSM RCR1.6 RSYNC Mode Select. 0 = frame mode (see the timing in Section 13) 1 = multiframe mode (see the timing in Section 13) RSIO RCR1.
DS2143/DS2143Q RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex) (MSB) Sa8S (LSB) Sa7S Sa6S Sa5S Sa4S SCLKM ESE – SYMBOL POSITION NAME AND DESCRIPTION Sa8S RCR2.7 Sa8 Bit Select. Set to one to report the Sa8 bit at the RLINK pin; set to zero to not report the Sa8 bit. Sa7S RCR2.6 Sa7 Bit Select. Set to one to report the Sa7 bit at the RLINK pin; set to zero to not report the Sa7 bit. Sa6S RCR2.5 Sa6 Bit Select.
DS2143/DS2143Q TSA1 TCR1.2 Transmit Signaling All Ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones TSM TCR1.1 TSYNC Mode Select. 0 = frame mode (see the timing in Section 13) 1 = CAS and CRC4 multiframe mode (see the timing in Section 13) TSIO TCR1.0 TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex) (MSB) Sa8S (LSB) Sa7S Sa6S Sa5S Sa4S – AEBE P34F SYMBOL POSITION NAME AND DESCRIPTION Sa8S TCR2.
DS2143/DS2143Q TG802 CCR.5 Transmit G.802 Enable. See Section 13 for details. 0 = do not force TCHBLK high during bit 1 of timeslot 26 1 = force TCHBLK high during bit 1 of timeslot 26 TCRC4 CCR.4 Transmit CRC4 Enable. 0 = CRC4 disabled 1 = CRC4 enabled RSM CCR.3 Receive Signaling Mode Select. 0 = CAS signaling mode 1 = CCS signaling mode RHDB3 CCR.2 Receive HDB3 Enable. 0 = HDB3 disabled 1 = HDB3 enabled RG802 CCR.1 Receive G.802 Enable. See Section 13 for details.
DS2143/DS2143Q The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2 pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively. RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex) (MSB) (LSB) – – – ESF ESE – FASRC CASRC SYMBOL POSITION NAME AND DESCRIPTION – RIR.7 – RIR.
DS2143/DS2143Q CRC4 SYNC COUNTER The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the DS2143 has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR.0=0). This counter is useful for determining the amount of time the DS2143 has been searching for synchronization at the CRC4 level. Annex B of CCITT G.
DS2143/DS2143Q ALARM CRITERIA Table 3 ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RSA1 (receive signaling all ones) over 16 consecutive frames (one full MF) timeslot 16 contains less than 3 zeros over 16 consecutive frames (one full MF) timeslot 16 contains 3 or more zeros G.732 4.2 RSA0 (receive signaling all zeros) over 16 consecutive frames (one full MF) timeslot 16 contains all zeros over 16 consecutive frames (one full MF) timeslot 16 contains at least a single one G.732 5.
DS2143/DS2143Q LOTC SR2.2 Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9 µs). Will force pin 34 high if enabled via TCR2.0. Based on RCLK. RCMF SR2.1 Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled. LORC SR2.0 Loss of Receive Clock. Set when the RCLK pin has not transitioned for at least 2 µs (3 µs ±1 µs).
DS2143/DS2143Q IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex) (MSB) RMF (LSB) RAF TMF SEC TAF SYMBOL POSITION RMF IMR2.7 Receive CAS Multiframe. 0 = interrupt masked 1 = interrupt enabled RAF IMR2.6 Receive Align Frame. 0 = interrupt masked 1 = interrupt enabled TMF IMR2.5 Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled SEC IMR2.4 One Second Timer. 0 = interrupt masked 1 = interrupt enabled TAF IMR2.3 Transmit Align Frame.
DS2143/DS2143Q BPVCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex) BPVCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex) (MSB) (LSB) BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 BPVCR2 BV15 BV14 BV13 BV12 BV11 BV10 BV9 BV8 BPVCR1 SYMBOL POSITION NAME AND DESCRIPTION BV15 BPVCR1.7 MSB of the bipolar violation count BV0 BPVCR2.
DS2143/DS2143Q additional bits from the TLINK pin. If the user wishes to pass the Sa bits through the DS2143 without them being altered, then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. Please see the timing diagrams and the transmit data flow diagram in Section 13 for examples. or CRC4 level; it will continue to count if loss of sync occurs at the CAS level. 6.
DS2143/DS2143Q SYMBOL POSITION NAME AND DESCRIPTION X RS1.0/1/3 Spare Bits Y RS1.2 Remote Alarm Bit (integrated and reported in SR1.6) A(1) RS2.7 Signaling Bit A for Channel 1 D(30) RS16.0 Signaling Bit D for Channel 30 Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.
DS2143/DS2143Q Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the DS2143 will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5) to know when to update the signaling bits.
DS2143/DS2143Q 9.0 CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/ TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
DS2143/DS2143Q 10.0 ELASTIC STORE OPERATION The DS2143 has an onboard two frame (512 bits) elastic store. This elastic store can be enabled via RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz (RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic store is enabled, then the user has the option of either providing a frame sync at the RFSYNC pin (RCR1.5=1) or having the RFSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.
DS2143/DS2143Q RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex) (MSB) (LSB) Si 1 A Sa4 Sa5 SYMBOL POSITION Si RNAF.7 International Bit. 1 RNAF.6 Frame Non–Alignment Signal Bit. A RNAF.5 Remote Alarm. Sa4 RNAF.4 Additional Bit 4. Sa5 RNAF.3 Additional Bit 5. Sa6 RNAF.2 Additional Bit 6. Sa7 RNAF.1 Additional Bit 7. Sa8 RNAF.0 Additional Bit 8.
DS2143/DS2143Q Sa5 TNAF.3 Additional Bit 5. Sa6 TNAF.2 Additional Bit 6. Sa7 TNAF.1 Additional Bit 7. Sa8 TNAF.0 Additional Bit 8. 12.0 LINE INTERFACE CONTROL FUNCTION LI_CS, LI_SCLK and LI_SDI pins respectively. This control function is driven off of the RCLK and it must be present for proper operation. Registers CRB1 and CRB2 can only be written to, they cannot be read from. Writes to these registers must be at least 20 µs apart. See Section 13 for timing information.
DS2143/DS2143Q RECEIVE SIDE 1.544 MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) SYSCLK RSER1 CHANNEL 23/31 CHANNEL 24/32 LSB MSB CHANNEL 1/2 LSB F MSB RSYNC2 RSYNC3 RCHCLK RCHBLK4 NOTES: 1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F–bit position is added (forced to one). 2. RSYNC is in the output mode (RCR1.5=0). 3. RSYNC is in the input mode (RCR1.5=1). 4.
DS2143/DS2143Q RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) RCLK RPOS, RNEG1 CHANNEL 1 LSB RSER1 Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 32 LSB MSB CHANNEL 1 LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB Sa4 Sa5 Sa6 Sa7 Sa8 RSYNC RCHCLK RCHBLK2 RLINK RLCLK3 RLCLK4 RLCLK5 NOTES: 1. There is a 6 RCLK delay from RPOS, RNEG to RSER. 2. RCHBLK is programmed to block channel 2. 3. RLINK is programmed to output the Sa4 bits. 4. RLINK is programmed to output the Sa4 and Sa8 bits.
DS2143/DS2143Q G.802 TIMING TIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 RSYNC/ TSYNC RCHCLK/ TCHCLK RCHBLK/ TCHBLK1 DETAIL RCLK/TCLK TIMESLOT 25 RSER/TSER TIMESLOT 26 LSB MSB RCHCLK/TCHCLK RCHBLK/TCHCLK NOTE: 1. RCHBLK/TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, during bit 1 of timeslot 26.
DS2143/DS2143Q TRANSMIT SIDE BOUNDARY TIMING TCLK CHANNEL 1 TSER1 TPOS, TNEG1 LSB Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 32 MSB LSB MSB CHANNEL 1 LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB TSYNC2 TSYNC3 TCHCLK TCHBLK4 TLCLK5 TLINK5 Don’t Care Don’t Care TLCLK6 TLINK6 Don’t Care NOTES: 1. There is a 5 TCLK delay from TSER to TPOS, and TNEG. 2. TSYNC is in the input mode (TCR1.0=0). 3. TSYNC is in the output mode (TCR1.0=1). 4. TCHBLK is programmed to block channel 2. 5.
DS2143/DS2143Q TRANSMIT SIDE TIMING FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 TSYNC1 TSYNC2 TCLK3 TLINK3 NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumbes both the CAS MF and the CRC4 begin with the align frame.
DS2143/DS2143Q DS2143 SYNCHRONIZATION FLOWCHART POWER UP RLOS=1 RLOS=1 FAS SYNC CRITERIA MET FASSA=0 RESYNC IF RCR1.1=0 INCREMENT CRC4 SYNC COUNTER; CRC4SA=0 8 MS TIME OUT CRC4 MULTIFRAME SEARCH (IF ENABLED VIA CCR.0) CRC4SA=1 CRC4 SYNC CRITERIA MET; CRC4SA=0; RESET CRC4 SYNC COUNTER SET FASRC (RIR.1) 031397 30/40 FAS RESYNC CRITERIA MET CHECK FOR FAS FRAMING ERROR (DEPENDS ON RCR1.2) CRC4 RESYNC CRITERIA MET CHECK FOR >=915 OUT OF 1000 CRC WORD ERRORS IF CRC4 IS ON (CCR.
DS2143/DS2143Q DS2143 TRANSMIT DATA FLOW TSER TAF TNAF 0 1 TIMESLOT 0 PASS–THROUGH (TCR1.6) TS0 1 0 Si BIT INSERTION CONTROL (TCR1.3) AIS GENERATION TLINK 0 TS15 0 1 Sa BIT INSERTION CONTROL (TCR2.3 THRU TCR2.7) 1 TRANSMIT SIGNALLING ALL ONES (TCR1.2) 0 1 TIMESLOT 16 SIGNALING INSERTION CONTROL (TCR1.5) TIDR 0 1 IDLE CODE INSERTION CONTROL (TIR1 TO TIR4) RECEIVE SIDE CRC4 ERROR DETECTOR 0 1 E–BIT GENERATION (TCR2.1) CRC4 MF AND CODE WORD GENERATION 0 1 KEY CRC4 ENABLE (CCR.
DS2143/DS2143Q ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DS2143/DS2143Q AC CHARACTERISTICS – PARALLEL PORT PARAMETER (0°C to 70°C; VDD = 5V + 10%) SYMBOL MIN tCYC 250 ns Pulse Width, DS Low or RD High PWEL 150 ns Pulse Width, DS High or RD Low PWEH 100 ns Input Rise/Fall Times tR, tF R/W Hold Time tRWH 10 ns R/W Setup Time Before DS High tRWS 50 ns CS Setup Time Before DS, WR or RD active tCS 20 ns CS Hold Time tCH 0 ns Read Data Hold Time tDHR 10 Write Data Hold Time tDHW 0 ns Muxed Address Valid to AS or ALE fall tASL
DS2143/DS2143Q INTEL WRITE AC TIMING tCYC PWASH ALE tASD RD tASED tASD PWEH PWEL WR tCH tCS CS tASL tDHW AD0-AD7 tAHL tDSW INTEL READ AC TIMING tCYC PWASH ALE tASD WR tASD tASED PWEH RD PWEL tCS tCH CS tDDR tASL AD0-AD7 tAHL 031397 34/40 tDHR
DS2143/DS2143Q MOTOROLA AC TIMING PWASH AS PWEH DS tASD tASED PWEL tCYC tRWS tRWH R/W tASL tDDR tDHR AD0-AD7 (READ) tAHL AD0-AD7 (WRITE) tCH tCS CS tASL tDSW tAHL tDHW 031397 35/40
DS2143/DS2143Q AC CHARACTERISTICS – TRANSMIT SIDE PARAMETER SYMBOL TCLK Period tP TCLK Pulse Width (0°C to 70°C; VDD = 5V + 10%) MIN TYP MAX 488 UNITS ns tCH 50 ns tCL 50 ns TSER, TSYNC, TLINK Setup to TCLK Falling tSU 25 ns TSER, TLINK Hold from TCLK Falling tHD 25 ns TCLK Rise/Fall Times tR, tF 25 ns Data Delay tDD 50 ns TSYNC Pulse Width tPW 50 ns (0°C to 70°C; VDD = 5V ± 10%) AC CHARACTERISTICS – RECEIVE SIDE PARAMETER RCLK and SYSCLK Period RCLK and SYSCLK Pulse Wi
DS2143/DS2143Q TRANSMIT SIDE AC TIMING tP tCL tF tR tCH TCLK tDD TPOS, TNEG TSER tHD tDD tSU TCHCLK tDD TCHBLK tDD TSYNC1 tPW tSU TSYNC2 tDD TLCLK3 tSU tHD TLINK3 NOTES: 1. TSYNC is in the output mode (TCR1.0=1). 2. TSYNC is in the input mode (TCR1.0=0). 3. No timing relationship between TSYNC and TLCLK/TLINK is implied.
DS2143/DS2143Q RECEIVE SIDE AC TIMING tP tR SYSCLK RCLK tCL tF tDD RSER RPOS, RNEG tHD tDD tSU RCHCLK tDD RCHBLK tDD RSYNC1 tPW tSU RSYNC2 tDD RLCLK3 tDD RLINK3 NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). 3. No timing relationship between RSYNC and RLCLK/RLINK is implied.
DS2143/DS2143Q DS2143 E1 CONTROLLER (600 MIL) 40–PIN DIP 40 B 1 D A E C F K G J H INCHES DIM MIN MAX A 2.040 2.070 B 0.530 0.560 C 0.145 0.155 D 0.600 0.625 E 0.015 0.040 F 0.120 0.140 G 0.090 0.110 H 0.625 0.675 J 0.008 0.012 K 0.015 0.
DS2143/DS2143Q DS2143 E1 CONTROLLER 44–PIN PLCC E E1 B N 1 .075 MAX D1 D D2 NOTE 1 B1 CH1 .150 MAX e1 C E2 A2 NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 CH1 0.042 0.048 D 0.685 0.695 D1 0.650 0.656 D2 0.590 0.630 E 0.685 0.695 E1 0.650 0.656 E2 0.590 0.630 e1 N 031397 40/40 0.
