Manual

DS2141A
021997 22/35
386–bit elastic buffer either fills or empties, a controlled
slip will occur. If th e buffer empties, then a full frame of
data (193 bits) will be repeated at RSER and the SR1.4
and RIR.3 bits will be set to a one. If the buffer fills, then
a full frame of data will be deleted and the SR1.4 and
RIR.4 bits will be set to a one.
10.2 Transmit Side
The transmit side elastic store can only be used if the
receive side elastic store is enabled. The operation of
the transmit elastic store is very similar to the receive
side; both have controlled slip operation and both c an
operate with either a 1.544 MHz or a 2.048 MHz
SYSCLK. When the transmit elastic store is enabled,
both the SYSCLK and RSYNC signals are shared by
both the elastic stores. Hence, they will have the same
backplane PCM frame and data structure. Controlled
slips in the transmit elastic store are reported in by set-
ting both RIR.3 and RIR.4.
11.0 RECEIVE MARK REGISTERS
The DS2141A has the ability to replace the incoming
data, on a channel–by–channel basis, with either an idle
code (7F Hex) or the digital milliwatt code, which is an
8–byte repeating pattern that represents a 1 KHz sine
wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7–bit
will determine which code is used. Each bit in the RMRs
represents a particular channel. If a bit is set to a 1, then
the receive data in that channel will be replaced with one
of the two codes. If a bit is set to 0, no replacement
occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (2Dh to 2Fh)
(MSB) (LSB)
CH8
CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 RMR3.7 Receive Mark Registers.
CH1 RMR1.0 0=do not affect the receive data associated with this channel.
1=replace the receive data associated with this channel with either the idle
code or the digital milliwatt code.
12.0 LINE INTERFACE CONTROL FUNCTION
The DS2141A can control line interface units that con-
tain serial ports. When Control Register Bytes 1 or 2
(CRB1, CRB2) are written to, the DS2141A will auto-
matically write this data serially (LSB first) into the line
interface by creating a chip select, serial clock and serial
data via the LI_CS
, LI_SCLK and LI_SDI pins respec-
tively. This control function is driven off of the RCLK;
therefore RCLK must be present for proper operation.
Registers CRB1 and CRB2 can only be written to, not
read from. Writes to these registers must be at least 20
µsec apart. See Section 13 for timing information.
CRB1: CONTROL REGISTER BYTE 1 (7Ch)
CRB2: CONTROL REGISTER BYTE 2 (7Dh)
(MSB) (LSB)
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
SYMBOL POSITION NAME AND DESCRIPTION
CR0 CRB1.0 LSB of Control Register Byte 1.
CR7 CRB2.7 MSB of Control Register Byte 2.
RMR1 (2D)
RMR2 (2E)
RMR3 (2F)
CRB1 (7C)
CRB2 (7D)