DS2141A DS2141A T1 Controller FEATURES PIN ASSIGNMENT • DS1/ISDN–PRI framing transceiver TCLK 1 40 VDD TSER 2 39 TSYNC TCHCLK 3 38 TLINK TPOS 4 37 TLCLK TNEG 5 36 INT1 AD0 6 35 INT2 • Extracts and inserts robbed–bit signaling AD1 7 • Programmable output clocks AD3 8 9 34 33 RLOS/LOTC AD2 AD4 AD5 • Frames to D4, ESF, and SLC–96 formats • Parallel control port • Onboard, dual two–frame elastic store slip buffers 32 TCHBLK RCHBLK 10 31 LI_CS 11 30 LI_CLK • 5V supp
DS2141A 1.0 INTRODUCTION come out of it unchanged. Once the T1 data has been framed to, the robbed–bit signaling data and FDL can be extracted. The 2–frame elastic stores can either be enabled or bypassed. The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface controller, and the parallel control port. See the block diagram below. On the receive side, the device will clock in the serial T1 stream via the RPOS and RNEG pins.
DS2141A DS2141A FEATURES • parallel control port • large error counters • onboard dual 2–frame elastic store • FDL support circuitry • robbed–bit signaling extraction and insertion • programmable output clocks • fully independent transmit and receive sections • frame sync generation • error–tolerant yellow and blue alarm detection • output pin test mode • payload loopback capability • SLC–96 support • remote loop up/down code detection • loss of transmit clock detection • loss of receive clock detection
DS2141A PIN SYMBOL TYPE DESCRIPTION 25 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If set to output frame boundaries, then via RCR2.5, RSYNC can also be set to output double–wide pulses on signaling frames. If the elastic store is enabled via the CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame boundary pulse is applied. See Section 13 for timing details.
DS2141A DS2141A REGISTER MAP ADDRESS R/W REGISTER NAME 20 R/W Status Register 1 21 R/W Status Register 2 22 R/W Receive Information Register 23 R Bipolar Violation/ESF Error Event Count Register 1 24 R Bipolar Violation/ESF Error Event Count Register 2 25 R CRC6 Count Register 1 26 R CRC6 Count Register 2.
DS2141A 2.0 PARALLEL PORT The DS2141A is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2141A can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details.
DS2141A RCR2: RECEIVE CONTROL REGISTER 2 (2Ch) (MSB) RCS (LSB) RZBTSI RSDW RSM RSIO RD4YM FSBE BPVCRS SYMBOL POSITION NAME AND DESCRIPTION RCS RCR2.7 Receive Code Select. 0=idle code (7F Hex). 1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex). RZBTSI RCR2.6 Receive Side ZBTSI Enable. 0=ZBTSI disabled. 1=ZBTSI enabled. RSDW RCR2.5 RSYNC Double–Wide. 0=do not pulse double–wide in signaling frames. 1=do pulse double–wide in signaling frames. (note: this bit must be set to 0 when RCR2.
DS2141A TCR1: TRANSMIT CONTROL REGISTER 1 (35h) (MSB) ODF (LSB) TFPT TCPT RBSE GB7S TLINK TBL TYEL SYMBOL POSITION NAME AND DESCRIPTION ODF TCR1.7 Output Data Format. 0=bipolar data at TPOS and TNEG. 1=NRZ data at TPOS; TNEG = 0. TFPT TCR1.6 Transmit Framing Pass Through. 0=Ft or FPS bits sourced internally. 1=Ft or FPS bits sampled at TSER during F–bit time. TCPT TCR1.5 Transmit CRC Pass Through. 0=source CRC6 bits internally. 1=CRC6 bits sampled at TSER during F–bit time. RBSE TCR1.
DS2141A TSDW TCR2.4 TSYNC Double–Wide. 0=do not pulse double–wide in signaling frames. 1=do pulse double–wide in signaling frames. (note: this bit must be set to 0 when TCR2.3 = 1 or when TCR2.2 = 0). TSM TCR2.3 TSYNC Mode Select. 0=frame mode (see the timing in Section 13). 1=multiframe mode (see the timing in Section 13). TSIO TCR2.2 TSYNC I/O Select. 0=TSYNC is an input. 1=TSYNC is an output. TD4YM TCR2.1 Transmit Side D4 Yellow Alarm Select. 0=0s in bit 2 of all channels.
DS2141A PAYLOAD LOOPBACK When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2141A. When PLB is enabled, the following will occur: 1.
DS2141A RSLC96 CCR2.1 Receive SLC–96 Enable. 0=SLC–96 disabled. 1=SLC–96 enabled. RFDL CCR2.0 Receive Zero Destuffer Enable. 0=zero destuffer disabled. 1=zero destuffer enabled. 4.0 STATUS AND INFORMATION REGISTERS There is a set of three registers that contain information on the current real time status of the DS2141A: Status Register 1 (SR1), Status Register 2 (SR2), and the Receive Information Register (RIR).
DS2141A SEFE RIR.2 Severely Errored Framing Event. Set when 2 out of 6 framing bits are received in error. B8ZS RIR.1 B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.2. FBE RIR.0 Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error. Note: If the transmit elastic store slips, both RIR.4 and RIR.3 will be set.
DS2141A SR2: STATUS REGISTER 2 (21h) (MSB) RMF (LSB) TMF SEC RFDL TFDL RMTCH RAF LORC SYMBOL POSITION NAME AND DESCRIPTION RMF SR2.7 Receive Multiframe. Set on receive multiframe boundaries. TMF SR2.6 Transmit Multiframe. Set on transmit multiframe boundaries. SEC SR2.5 One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every three seconds. RFDL SR2.4 Receive FDL Buffer Full.
DS2141A RCL IMR1.1 Receive Carrier Loss. 0=interrupt masked. 1=interrupt enabled. RLOS IMR1.0 Receive Loss of Sync. 0=interrupt masked. 1=interrupt enabled. IMR2: INTERRUPT MASK REGISTER 2 (6Fh) (MSB) RMF (LSB) TMF SEC RFDL TFDL RMTCH SYMBOL POSITION RMF IMR2.7 Receive Multiframe. 0=interrupt masked. 1=interrupt enabled. TMF IMR2.6 Transmit Multiframe. 0=interrupt masked. 1=interrupt enabled. SEC IMR2.5 One Second Timer. 0=interrupt masked. 1=interrupt enabled. RFDL IMR2.
DS2141A 5.0 ERROR COUNT REGISTERS There is a set of three counters in the DS2141A that record bipolar violations, errors in the CRC6 code words, and frame bit errors. Each of these three counters is automatically updated on one–second boundaries as determined by the one–second timer in Status Register 2 (SR2.5). Hence, these registers contain performance data from the previous second. The user can use the interrupt from the one–second timer to determine when to read these registers.
DS2141A FECR: FRAME ERROR COUNT REGISTER (27h) (MSB) FE7 (LSB) FE6 FE5 FE4 FE3 SYMBOL POSITION FE7 FECR.7 MSB of the Frame Error count. FE0 FECR.0 LSB of the Frame Error count. FE1 FE0 NAME AND DESCRIPTION The Frame Error Count Register (FECR) is a 8–bit counter that records either errors in the framing pattern. The FECR will count individual bit errors in the ESF framing pattern (...001011...) if the device is set into the ESF framing mode (CCR2.
DS2141A RFDL: RECEIVE FDL REGISTER (28h) (MSB) RFDL7 (LSB) RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 SYMBOL POSITION RFDL7 RFDL.7 MSB of the Received FDL Code. RFDL0 RFDL.0 LSB of the Received FDL Code. RFDL1 RFDL0 NAME AND DESCRIPTION The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs–bits. The LSB is received first.
DS2141A TFDL: TRANSMIT FDL REGISTER (7Eh) (MSB) TFDL7 (LSB) TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 SYMBOL POSITION TFDL7 TFDL.7 MSB of the FDL code to be transmitted. TFDL0 TFDL.0 LSB of the FDL code to be transmitted. TFDL1 TFDL0 NAME AND DESCRIPTION The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. 7.
DS2141A Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two framing bits per channel (A and B). In the D4 framing mode, the DS2141A will replace the C and D signaling bit positions with the A and B signaling bits from the previous multiframe.
DS2141A TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (39h to 3Bh) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TTR1 (39) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TTR2 (3A) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TTR3 (3B) SYMBOL POSITION CH24 CH1 TTR3.7 TTR1.0 NAME AND DESCRIPTION Transmit Transparency Registers. 0=this DS0 channel is not transparent. 1=this DS0 channel is transparent.
DS2141A 9.0 CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user–programmable outputs that can be forced either high or low during indi- vidual channels. These outputs can be used to block clocks to a USART or LAPD controller in Fractional T1, E1 to T1, or ISDN–PRI applications.
DS2141A 386–bit elastic buffer either fills or empties, a controlled slip will occur. If th e buffer empties, then a full frame of data (193 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a one. 10.2 Transmit Side The transmit side elastic store can only be used if the receive side elastic store is enabled.
DS2141A 13.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RSYNC1 RSYNC2 RSYNC3 RLCLK RLINK4 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double–wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double–wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. RLINK data (S–bit) is updated one bit prior to even frames and held for two frames.
DS2141A 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE(S) ENABLED) SYSCLK CHANNEL 23 TSER/ RSER CHANNEL 24 LSB MSB CHANNEL 1 LSB F MSB RSYNC1 RSYNC2 RCHCLK RCHBLK3 NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24. 2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE(S) ENABLED) SYSCLK CHANNEL 31 TSER/ RSER1 CHANNEL 32 LSB MSB CHANNEL 1 LSB RSYNC2 RSYNC3 RCHCLK RCHBLK4 NOTES: 1.
DS2141A RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED) RCLK RPOS1, RNEG LSB CHANNEL 1 F CHANNEL 2 MSB LSB MSB CHANNEL 23 LSB MSB CHANNEL 24 TSER/ RSER1 CHANNEL 1 LSB MSB LSB F MSB RSYNC RCHCLK RCHBLK2 RLCLK RLINK NOTES: 1. There is a 13 RCLK delay from RPOS, RNEG to RSER. 2. RCHBLK is programmed to block Channel 24. TRANSMIT SIDE D4 TIMING FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 TSYNC1 TSYNC2 TSYNC3 TLCLK TLINK4 NOTES: 1.
DS2141A TRANSMIT SIDE ESF TIMING FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TSYNC1 TSYNC2 TSYNC3 TLCLK4 TLINK5 TLCLK6 TLINK7 NOTES: 1. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double–wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.4=1). 4. ZBTSI mode disabled (TCR2.5=0). 5.
DS2141A TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED) TCLK TSER1 TPOS, TNEG1 CHANNEL 1 LSB F CHANNEL 2 MSB LSB MSB LSB MSB CHANNEL 23 CHANNEL 24 CHANNEL 1 LSB MSB LSB F MSB TSYNC2 TSYNC3 TCHCLK TCHBLK4 TLCLK Don’t Care TLINK NOTES: 1. There is a 10 TCLK delay from TSER to TPOS, TNEG. 2. TSYNC is in the input mode (TCR2.2=0). 3. TSYNC is in the output mode (TCR2.2=1). 4. TCHBLK is programmed to block Channel 1.
DS2141A ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DS2141A AC CHARACTERISTICS – PARALLEL PORT PARAMETER (0°C to 70°C; VDD = 5V + 10%) SYMBOL MIN tCYC 250 ns Pulse Width, DS Low or RD High PWEL 150 ns Pulse Width, DS High or RD Low PWEH 100 ns Input Rise/Fall Times tR, tF R/W Hold Time tRWH 10 ns R/W Setup Time Before DS High tRWS 50 ns CS Setup Time Before DS, WR or RD active tCS 20 ns CS Hold Time tCH 0 ns Read Data Hold Time tDHR 10 Write Data Hold Time tDHW 0 ns Muxed Address Valid to AS or ALE fall tASL 20 ns
DS2141A INTEL READ AC TIMING AC TIMING tCYC PWASH ALE tASD WR tASD tASED PWEH PWEL RD tCS tCH CS tDDR tASL tDHR AD0–AD7 tAHL INTEL WRITE AC TIMING tCYC PWASH ALE tASD RD WR tASD tASED PWEH PWEL tCH tCS CS tASL tDHW AD0–AD7 tAHL 021997 30/35 tDSW
DS2141A MOTOROLA AC TIMING PWASH AS PWEH DS tASD tASED PWEL tCYC tRWS tRWH R/W tASL tDDR tDHR AD0–AD7 (READ) tAHL AD0–AD7 (WRITE) tCH tCS CS tASL tDSW tDHW tAHL (0°C to 70°C; VDD = 5V ± 10%) AC CHARACTERISTICS – RECEIVE SIDE PARAMETER RCLK and SYSCLK Period RCLK and SYSCLK Pulse Width SYMBOL MIN tP TYP MAX 648 UNITS ns tCH 50 ns tCL 50 ns RPOS, RNEG, Setup to RCLK Falling tSU 25 ns RPOS, RNEG, Hold from RCLK Falling tHD 25 ns RCLK Rise/Fall Times NOTES tR, tF 25
DS2141A RECEIVE SIDE AC TIMING tP tR SYSCLK RCLK tCL tF tDD F–BIT RSER RPOS, RNEG tHD tDD tSU RCHCLK tDD RCHBLK tDD RSYNC1 tPW tSU RSYNC2 tDD RLCLK tDD RLINK NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1).
DS2141A AC CHARACTERISTICS – TRANSMIT SIDE PARAMETER SYMBOL TCLK Period tP TCLK Pulse Width (0°C to 70°C; VDD = 5V + 10%) MIN TYP MAX UNITS 648 tCH 50 ns tCL 50 ns TSER, TSYNC, TLINK Setup to TCLK Falling tSU 25 ns TSER, TLINK Hold from TCLK Falling tHD 25 ns TCLK Rise/Fall Times tR, tF Data Delay tDD TSYNC Pulse Width tPW NOTES ns 25 ns 75 ns 50 ns TRANSMIT SIDE AC TIMING tP tCL tF tR tCH TCLK tDD TPOS, TNEG TSER F–BIT tHD tDD tSU TCHCLK tDD TCHBLK tDD TSYNC
DS2141A DS2141A T1 CONTROLLER (600 MIL) 40–PIN DIP 40 B 1 D A E C F K G INCHES DIM MIN MAX A 2.040 2.070 B 0.530 0.560 C 0.145 0.155 D 0.600 0.625 E 0.015 0.040 F 0.120 0.140 G 0.090 0.110 H 0.625 0.675 J 0.008 0.012 K 0.015 0.
DS2141A DS2141AQ T1 CONTROLLER 44–PIN PLCC E E1 B N 1 .075 MAX D1 D D2 NOTE 1 B1 CH1 .150 MAX e1 C A E2 A2 A1 NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM. MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 CH1 0.042 0.048 D 0.685 0.695 D1 0.650 0.656 D2 0.590 0.630 E 0.685 0.695 E1 0.650 0.656 E2 0.590 0.630 e1 N 0.
