Owner's manual

DS1957
20 of 25
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 8. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS1957 to the master
by triggering a delay circuit in the DS1957. During write time slots, the delay circuit determines when
the DS1957 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS1957 will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1”, the DS1957 will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 7
t
RSTH
tRSTL
tR
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tPDH
tPDL
RESISTOR
MASTER
DS1954
MASTER RX PRESENCE PULSE"MASTER TX RESET PULSE"
Regular Speed Overdrive speed
480
µ s < t
RSTL
< 1 * 48 µ s < t RSTL
< 80 µ s
480
µ s < t RSTH
< 1** 48 µ s < t RSTH
< 1**
15
µ s < t PDH
< 60 µ s 2 µ s < t PDH
< 6 µ s
60
µ s < t PDL
< 240 µ s 8 µ s < t PDL
< 24 µ s
* IN ORDER NOT TO MASK INTERRUPT SIGNALLING BY OTHER DEVICES ON THE 1-WIRE BUS, tRSTL + tR SHOULD
ALWAYS BE LESS THAN 960
µ s
** INCLUDES RECOVERY TIME
READ/WRITE TIMING DIAGRAM Figure 8
WRITE-ONE TIME SLOT
60
=
==
=
µ
µµ
µ
s
t
REC
t
LOW1
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
15
µ
µµ
µ
s
DS1957
SAMPLING WINDOW
t
SLOT
Regular Speed
60
µ
µµ
µ
s< t
SLOT
< 120
µ
µµ
µ
s
1
µ
µµ
µ
s< t
LOW1
< 15
µ
µµ
µ
s
1
µ
µµ
µ
s< t
REC
<1
Overdrive Speed
6
µ
µµ
µ
s< t
SLOT
< 16
µ
µµ
µ
s
1
µ
µµ
µ
s< t
LOW1
< 2
µ
µµ
µ
s
1
µ
µµ
µ
s< t
REC
<1
(OD: 2
µ
µµ
µ
s)
(OD: 6
µ
µµ
µ
s)