Instruction Manual

48 _____________________________________________________________________________________
DS1876
SFP Controller with Dual LDD Interface
Table 02h, Register 89h: CNFGB
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY Common A2h and B2h memory location
MEMORY TYPE Nonvolatile (SEE)
89h IN1C INVOUT1 ALATCH2 QTLATCH2 WLATCH2 ALATCH1 QTLATCH1 WLATCH1
BIT 7 BIT 0
BIT 7
IN1C: IN1 software control bit (see Figure 10).
0 = IN1 pin’s logic controls OUT1 pin.
1 = OUT1 is active (bit 6 defines the polarity).
BIT 6
INVOUT1: Inverts the active state for OUT1 (see Figure 10).
0 = Noninverted.
1 = Inverted.
BIT 5
ALATCH2: ADC alarm’s comparison latch for transmitter 2. Latches alarms in Lower Memory,
Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 4
QTLATCH2: QT’s comparison latch for transmitter 2. Latches QT alarms in Lower Memory,
Registers 72h–73h and 76h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
BIT 3
WLATCH2: ADC warning’s comparison latch for transmitter 2. Latches warnings in Lower Memory,
Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
BIT 2
ALATCH1: ADC alarm’s comparison latch for transmitter 1. Latches alarms in Lower Memory,
Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 1
QTLATCH1: QT’s comparison latch for transmitter 1. Latches QT alarms in Lower Memory,
Registers 72h–73h and 76h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
BIT 0
WLATCH1: ADC warning’s comparison latch for transmitter 1. Latches warnings in Lower Memory,
Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.