User guide

DS1875
PON Triplexer and SFP Controller
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Table 02h, Register 89h: CONFIG
FACTORY DEFAULT 00h
READ ACCESS PW2
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
89h FETG DIR TX-F LEN M3QT LEN ASEL BOLFS RSSI_FC RSSI_FF EN5TO8B
BIT 7 BIT 0
Configure the memory location and the polarity of the digital outputs.
BIT 7
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
0 = (Default) Under normal operation, FETG is pulled low.
1 = Under normal operation, FETG is pulled high.
BIT 6
TX-F LEN: The TX-F output pin always reflects the wired-OR of all TX-F enabled alarm states. This
bit enables the latching of the alarm state for the TX-F output pin.
0 = (Default) Not latched.
1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If the V
CC
alarm is
enabled for either FETG or TX-F, then latching is disabled until after the first V
CC
measurement is
made above the V
CC
ALARM LO set point to allow for proper operation during slow power-on
cycles.
BIT 5
M3QT LEN: This bit enables the latching of the alarm for the M3QT.
0 = (Default) Not latched.
1 = The alarm bit is latched until cleared by setting the M3QT RESET bit (Byte 78h).
BIT 4
ASEL: Address select.
0 = (Default) Device address of A2h.
1 = Device address is equal to the value found in the DEVICE ADDRESS byte (Table 02h, 8Ch).
BIT 3
BOLFS: Bias open-loop full scale.
0 = (Default) Full scale is 600μA.
1 = Full scale is 1.2mA.
BITS 2:1
RSSI_FC and RSSI_FF: RSSI force coarse and RSSI force fine. Control bits for RSSI mode of
operation on the MON3 conversion.
00b = (Default) Normal RSSI mode of operation.
01b = The fine settings of scale and offset are used for MON3 conversions.
10b = The coarse settings of scale and offset are used for MON3 conversions.
11b = Normal RSSI mode of operation.
BIT 0
EN5TO8B: This bit enables MON5–MON8 conversion (voltage of D0–D3 pins).
0 = (Default) Temperature, V
CC
, and MON1–MON8 conversions are enabled.
1 = Temperature, V
CC
, and MON1–MON4 conversions are enabled.