Owner's manual

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General Description

The DS1874 controls and monitors all functions for SFF,

SFP, and SFP+ modules including all SFF-8472 func-

tionality. The combination of the DS1874 with the

MAX3798/MAX3799 laser driver/limiting amplifier pro-

vides APC loop, modulation current control, and eye

safety functionality. The DS1874 continuously monitors

for high output current, high bias current, and low and

high transmit power to ensure that laser shutdown for

eye safety requirements are met without adding external

components. Six ADC channels monitor V

, tempera-

ture, and four external monitor inputs (MON1–MON4)

that can be used to meet all monitoring requirements.

MON3 is differential with support for common mode to

. Two digital-to-analog (DAC) outputs with tempera-

ture-indexed lookup tables (LUTs) are available for addi-

tional monitoring and control functionality.

Applications

SFF, SFP, and SFP+ Transceiver Modules

Features

♦ Meets All SFF-8472 Control and Monitoring

Requirements

♦ Laser Bias Controlled by APC Loop and

Temperature LUT to Compensate for Tracking

Error

♦ Laser Modulation Controlled by Temperature LUT

♦ Six Analog Monitor Channels: Temperature, V

MON1–MON4

MON1–MON4 Support Internal and External

Calibration

Scalable Dynamic Range

Internal Direct-to-Digital Temperature Sensor

Alarm and Warning Flags for All Monitored

Channels

♦ Two 9-Bit Delta-Sigma Outputs with 36 Entry

Temperature LUTs

♦ Digital I/O Pins: Five Inputs, Five Outputs

♦ Comprehensive Fault-Measurement System with

Maskable Laser Shutdown Capability

♦ Flexible, Two-Level Password Scheme Provides

Three Levels of Security

♦ 256 Additional Bytes Located at A0h Slave

Address

♦ I

C-Compatible Interface

♦ 3-Wire Master to Communicate with the MAX3798/

MAX3799 Laser Driver/Limiting Amplifier

♦ +2.85V to +3.9V Operating Voltage Range

♦ -40°C to +95°C Operating Temperature Range

♦ 28-Pin TQFN (5mm x 5mm) Package

DS1874

________________________________________________________________

Maxim Integrated Products

THIN QFN

(5mm

5mm

0.8mm)

TOP VIEW

SCL

TXF

LOS

IN1

TXD

RSELOUT

DAC2

REFIN

GND

MON2

SCLOUT

4567

2021 19 17 16 15

SDAOUT

LOSOUT

MON3P

MON4

TXDOUT

RSEL

SDA

DAC1

OUT1

GND

CSELOUT

MON3N

MON1

N.C.

DS1874

*EP

*EXPOSED PAD.

Pin Configuration

Ordering Information

19-4691; Rev 0; 6/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

DS1874T+ -40°C to +95°C 28 TQFN-EP*

DS1874T+T&R -40°C to +95°C 28 TQFN-EP*

SFP+ Controller with Digital LDD Interface

Summary of content (88 pages)

PAGE 1
9-4691; Rev 0; 6/09 SFP+ Controller with Digital LDD Interface The DS1874 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality. The combination of the DS1874 with the MAX3798/MAX3799 laser driver/limiting amplifier provides APC loop, modulation current control, and eye safety functionality.
PAGE 2
DS1874 SFP+ Controller with Digital LDD Interface TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SFP+ Controller with Digital LDD Interface Transmit Fault (TXF) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3-Wire Master for Controlling the MAX3798/MAX3799 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
DS1874 SFP+ Controller with Digital LDD Interface LIST OF FIGURES Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 2. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 3. TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SFP+ Controller with Digital LDD Interface Operating Temperature Range ...........................-40°C to +95°C Programming Temperature Range .........................0°C to +95°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. *Subject to not exceeding +6V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 6
DS1874 SFP+ Controller with Digital LDD Interface DAC1, DAC2 ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) SYMBOL CONDITIONS TYP MAX UNITS f OSC 5 MHz fDS f OSC/2 MHz VREFIN Minimum 0.1μF to GND Output Range 2 VCC V 0 VREFIN V 9 Bits 35 100 TYP MAX UNITS See the Delta-Sigma Outputs (DAC1 and DAC2) section for details.
PAGE 7
SFP+ Controller with Digital LDD Interface DS1874 DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL T ERR CONDITIONS -40°C to +95°C MIN TYP -3 MAX UNITS +3 °C MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.
PAGE 8
DS1874 SFP+ Controller with Digital LDD Interface I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See Figure 17.
PAGE 9
SFP+ Controller with Digital LDD Interface SDA = SCL = VCC 2.6 +95°C 2.5 2.3 -40°C 2.1 +25°C 1.9 VCC = 3.9V 2.5 2.4 2.3 VCC = 2.85V VCC = 3.3V 2.2 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V 0.8 0.6 MON1–MON4 INL (LSB) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 2.7 1.0 DS1874 toc02 DS1874 toc01 SDA = SCL = VCC 2.9 MON1–MON4 INL SUPPLY CURRENT vs. TEMPERATURE 2.7 DS1874 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.4 0.2 0 -0.2 -0.4 -0.6 1.7 2.1 1.5 2.0 3.10 3.35 3.60 3.
PAGE 10
SFP+ Controller with Digital LDD Interface DS1874 Pin Description 10 PIN NAME 1 RSELOUT FUNCTION 2 SCL I2C Serial-Clock Input 3 SDA I2C Serial-Data Input/Output Rate-Select Output 4 TXF Transmit-Fault Input and Output. The output is open drain. 5 LOS Loss-of-Signal Input 6 IN1 Digital Input. General-purpose input with AS1 in SFF-8079 or RS1 in SFF-8431.
PAGE 11
SFP+ Controller with Digital LDD Interface REFIN VCC MAIN MEMORY EEPROM/SRAM VCC SDA SCL I2C INTERFACE ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY 9-BIT DELTA-SIGMA DAC1 9-BIT DELTA-SIGMA DAC2 EEPROM 256 BYTES AT A0h SDAOUT VCC 3-WIRE INTERFACE 13-BIT ADC MON1 MON3P MON3N CSELOUT APC INTEGRATOR ANALOG MUX MON2 SCLOUT 8-BIT QTs MON4 TEMPERATURE SENSOR TXF POWER-ON ANALOG INTERRUPT VCC SEE FIGURE 12 TXD TXDOUT RSELOUT RSEL OUT1 I
PAGE 12
SFP+ Controller with Digital LDD Interface DS1874 Typical Operating Circuit +3.
PAGE 13
SFP+ Controller with Digital LDD Interface ACRONYM DEFINITION ADC Analog-to-Digital Converter AGC Automatic Gain Control APC Automatic Power Control APD Avalanche Photodiode ATB Alarm Trap Bytes BM Burst Mode DAC Digital-to-Analog Converter LOS Loss of Signal LUT Lookup Table NV Nonvolatile QT Quick Trip TE Tracking Error TIA MODULATION Control Transimpedance Amplifier ROSA Receiver Optical Subassembly SEE Shadowed EEPROM SFF Small Form Factor Document Defining Register Map
PAGE 14
DS1874 SFP+ Controller with Digital LDD Interface BIAS and MODULATION Control During Power-Up However, the BIAS MAX alarm is monitored during this time to prevent the BIAS register from exceeding IBIASMAX. During the bias current initialization, the BIAS register is not allowed to exceed IBIASMAX. If this occurs during the ISTEP sequence, then the binary search routine is enabled. If IBIASMAX is exceeded during the binary search, the next smaller step is activated.
PAGE 15
SFP+ Controller with Digital LDD Interface If TXD is asserted (logic 1) during normal operation, the outputs are disabled within tOFF. When TXD is deasserted (logic 0), the DS1874 sets the MODULATION register with the value associated with the present temperature, and initializes the BIAS register using the same search algorithm as done at startup. When asserted, soft TXD (TXDC) (Lower Memory, Register 6Eh) would allow a software control identical to the TXD pin (see Figure 3).
PAGE 16
DS1874 SFP+ Controller with Digital LDD Interface ignored until the end of the 3-wire communication that updates the MAX3798/MAX3799’s BIAS DAC, plus an additional 16 sample periods (tREP). Monitors and Fault Detection Monitors Monitoring functions on the DS1874 include five quick-trip comparators and six ADC channels. This monitoring combined with the alarm enables (Table 01h/05h) determines when/if the DS1874 turns off the MAX3798/ MAX3799 DACs and triggers the TXF and TXDOUT outputs.
PAGE 17
SFP+ Controller with Digital LDD Interface DS1874 ONE ROUND-ROBIN ADC CYCLE TEMP VCC MON1 MON2 MON3 MON4 TEMP tRR NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC ALARM LOW THRESHOLD. Figure 5. ADC Round-Robin Timing VCC MON3P DS1874 ADC 100Ω MON3N ROSA Figure 6.
PAGE 18
DS1874 SFP+ Controller with Digital LDD Interface Table 4. MON3 Hysteresis Threshold Values MON3 TIMESLICE NUMBER OF RIGHT-SHIFTS PERFORM FINEMODE CONVERSION DID PRIOR MON3 TIMESLICE RESULT IN A COARSE CONVERSION? (LAST RSSI = 1?) Y N N WAS CURRENT FINEMODE CONVERSION ≥ 93.75% OF FS? FINE MODE MAX (hex) COARSE MODE MIN* (hex) 0 FFF8 F000 1 7FFC 7800 2 3FFE 3C00 3 1FFF 1E00 4 0FFF 0F00 5 07FF 0780 6 03FF 03C0 7 01FF 01E0 *This is the minimum reported coarse-mode conversion.
PAGE 19
SFP+ Controller with Digital LDD Interface is timed (within 500µs) to go to 0, at which point the part is fully functional. For all device addresses sourced from EEPROM (Table 02h, Register 8Ch), the default device address is A2h until VCC exceeds POA, allowing the device address to be recalled from the EEPROM.
PAGE 20
DS1874 SFP+ Controller with Digital LDD Interface 3.24kΩ 3.24kΩ DAC1/DAC2 OUTPUT 0.01μF 0.01μF DS1874 is either manually controlled or controlled using a temperature-indexed LUT. A delta-sigma is a digital output using pulse-density modulation. It provides much lower output ripple than a standard digital PWM output given the same clock rate and filter components. Before tINIT, the DAC1 and DAC2 outputs are high impedance.
PAGE 21
SFP+ Controller with Digital LDD Interface LOS, LOSOUT By default (LOSC = 1, Table 02h, Register 89h), the LOS pin is used to convert a standard comparator output for loss of signal (LOS) to an open-collector output. This means the mux shown in the Block Diagram by default selects the LOS pin as the source for the LOSOUT output transistor. The output of the mux can be read in the STATUS byte (Table 01h, Register 6Eh) as the RXL bit.
PAGE 22
DS1874 SFP+ Controller with Digital LDD Interface IN1S OUT1 INVOUT1 IN1C IN1 RSELS RSELOUT RSELC Die Identification RSEL LOSC Transmit Fault (TXF) Output TXF can be triggered by all alarms, warnings, and quick trips (Figure 12). The six ADC alarms, warnings, and the LOS quick trips require enabling (Table 01h/05h, Registers F8h and FDh). See Figures 14a and 14b for nonlatched and latched operation.
PAGE 23
SFP+ Controller with Digital LDD Interface BIT NAME 15:9 Address 8 RWN 0: write; 1: read 7:0 Data 8-bit read or write data Figure 15 shows the 3-wire interface timing. Figure 16 shows the 3-wire state machine. See the 3-Wire Digital Interface Specification table for more information. DESCRIPTION DS1874 and MAX3798/MAX3799 Communication 7-bit internal register address Normal Operation Write Mode (RWN = 0): The master generates 16 clock cycles at SCLOUT in total.
PAGE 24
DS1874 SFP+ Controller with Digital LDD Interface RESET FLAGS HERE POR READ TXPOR1 UPDATE MODULATION YES READ TXPOR3 YES TX_POR = 1? TXDIS = 1? NO YES READ TXPOR4 SET TXD FLAG HERE TXD_LATCHED = 1 NO WRITE MOD, BIAS = 00 UPDATE CTRL TX_POR = = 1? TX_POR = = 1? NO TXD = = 0? TXD HIGH_STDBY 1011 NO START APC LOOP YES TXD = = 0? READ/WRITE MANMODE MAN_MODE_RDWR = 1? YES APC_BINARY = = 1? NO STROBE SET RTXPOR2_FLAG HERE TXD_FLAG = = 1 OR TXDIS = 1 OR RTXPOR2 FLAG NO READ TXPOR2 NO
PAGE 25
SFP+ Controller with Digital LDD Interface The 3-wire control registers include the following: • RXCTRL1 • RXCTRL2 • SET_CML • SET_LOS • TXCTRL • IMODMAX • IBIASMAX • SET_PWCTRL • SET_TXDE The control registers are first written when VCC exceeds POA. They are also written if the MAX3798/MAX3799 TX_POR bit is set high (visible in 3W TXSTAT1, bit 7). In the MAX3798/MAX3799, this bit is “sticky” (latches high and is cleared on a read). They are also updated on a rising edge of TXD.
PAGE 26
DS1874 SFP+ Controller with Digital LDD Interface I2C Communication I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master’s request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states.
PAGE 27
SFP+ Controller with Digital LDD Interface Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition.
PAGE 28
DS1874 SFP+ Controller with Digital LDD Interface TYPICAL I2C WRITE TRANSACTION MSB START 1 MSB LSB 0 1 0 0 0 SLAVE ADDRESS* 1 R/W SLAVE ACK b7 LSB b6 b5 b4 b3 b2 b1 MSB SLAVE ACK b0 b7 LSB b6 b5 b4 REGISTER ADDRESS READ/ WRITE b3 b2 b1 b0 SLAVE ACK STOP DATA *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY.
PAGE 29
SFP+ Controller with Digital LDD Interface Many NV memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM that are controlled by the SEEB bit in Table 02h, Register 80h. The DS1874 incorporates shadowed-EEPROM memory locations for key memory addresses that can be written many times. By default the shadowed-EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM.
PAGE 30
DS1874 SFP+ Controller with Digital LDD Interface Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more information about each of these bytes see the corresponding register description.
PAGE 31
SFP+ Controller with Digital LDD Interface TABLE 01h WORD 0 WORD 1 WORD 2 WORD 3 ROW (hex) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F 80–BF <7>EEPROM EE EE EE EE EE EE EE EE C0–F7 <8>EEPROM EE EE EE EE EE EE EE EE <8>ALARM ALARM EN3 ALARM EN2 ALARM EN1 ALARM EN0 WARN EN3 WARN EN2 RESERVED RESERVED F8 ENABLE The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h with the
PAGE 32
DS1874 SFP+ Controller with Digital LDD Interface Table 02h Register Map TABLE 02h ROW (hex) ROW NAME WORD 0 BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B BYTE 4/C <4>MODULATION WORD 3 BYTE 5/D BYTE 6/E 80 <0>CONFIG0 <8>MODE <4>TINDEX 88 <8>CONFIG1 SAMPLE RATE CNFGA 90 <8>SCALE0 RESERVED VCC SCALE MON1 SCALE MON2 SCALE 98 <8>SCALE1 MON3 FINE SCALE MON4 SCALE MON3 COARSE SCALE RESERVED A0 <8>OFFSET0 RESERVED VCC OFFSET MON1 OFFSET MON2 OFFSET A8 <8>OFFSET1 B0 <9
PAGE 33
SFP+ Controller with Digital LDD Interface TABLE 04h (MODULATION LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (hex) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F 80–C7 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD Table 05h Register Map TABLE 05h ROW (hex) 80–F7 F8 WORD 0 ROW NAME BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 WORD 3 BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY <8>ALARM ALARM
PAGE 34
DS1874 SFP+ Controller with Digital LDD Interface Table 07h Register Map TABLE 07h (DAC1 LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (hex) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E 80–9F <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 A0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 RESERVED RESERVED RESERVED RESERVED BYTE 7/F Table 08h Register Map TABLE 08h (DAC2 LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (hex) ROW NAME 80–9F <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2
PAGE 35
SFP+ Controller with Digital LDD Interface Lower Memory, Register 00h–01h: TEMP ALARM HI Lower Memory, Register 04h–05h: TEMP WARN HI FACTORY DEFAULT 7FFFh READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) MEMORY TYPE Nonvolatile (SEE) 00h, 04h S 26 25 24 23 22 21 20 01h, 05h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Temperature measurement updates above this two’s complement threshold set corresponding alarm or warning bits.
PAGE 36
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 08h–09h: VCC ALARM HI Lower Memory, Register 0Ch–0Dh: VCC WARN HI Lower Memory, Register 10h–11h: MON1 ALARM HI Lower Memory, Register 14h–15h: MON1 WARN HI Lower Memory, Register 18h–19h: MON2 ALARM HI Lower Memory, Register 1Ch–1Dh: MON2 WARN HI Lower Memory, Register 20h–21h: MON3 ALARM HI Lower Memory, Register 24h–25h: MON3 WARN HI Lower Memory, Register 28h–29h: MON4 ALARM HI Lower Memory, Register 2Ch–2Dh: MON4 WARN HI 08h, 0C
PAGE 37
SFP+ Controller with Digital LDD Interface 0Ah, 0Eh, 12h, 16h, 1Ah, 1Eh, 22h, 26h, 2Ah, 2Eh 0Bh, 0Fh, 13h, 17h, 1Bh, 1Fh, 23h, 27h, 2Bh, 2Fh DS1874 Lower Memory, Register 0Ah–0Bh: VCC ALARM LO Lower Memory, Register 0Eh–0Fh: VCC WARN LO Lower Memory, Register 12h–13h: MON1 ALARM LO Lower Memory, Register 16h–17h: MON1 WARN LO Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO Lower Memory, Register 1Eh–1Fh: MON2 WARN LO Lower Memory, Register 22h–23h: MON3 ALARM LO Lower Memory, Register 26h–27h: MON3 WARN LO
PAGE 38
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 30h–5Fh: EE 30h to 5Fh FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) MEMORY TYPE Nonvolatile (EE) EE EE EE EE EE EE EE BIT 7 EE BIT 0 PW2 level access-controlled EEPROM.
PAGE 39
SFP+ Controller with Digital LDD Interface DS1874 Lower Memory, Register 62h–63h: VCC VALUE Lower Memory, Register 64h–65h: MON1 VALUE Lower Memory, Register 66h–67h: MON2 VALUE Lower Memory, Register 68h–69h: MON3 VALUE Lower Memory, Register 6Ah–6Bh: MON4 VALUE 62h, 64h, 66h, 68h, 6Ah 63h, 65h, 67h, 69h, 6Bh POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Left-justified unsigned voltag
PAGE 40
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE Write Access 6Eh X0XX 0XXXb READ ACCESS All WRITE ACCESS See below MEMORY TYPE Volatile N/A All N/A All All N/A N/A N/A TXDS TXDC IN1S RSELS RSELC TXF RXL RDYB BIT 7 40 BIT 0 BIT 7 TXDS: TXD Status Bit. Reflects the logic state of the TXD pin (read only). 0 = TXD pin is logic-low. 1 = TXD pin is logic-high. BIT 6 TXDC: TXD Software Control Bit.
PAGE 41
SFP+ Controller with Digital LDD Interface 6Fh POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All and DS1874 Hardware MEMORY TYPE Volatile TEMP RDY VCC RDY MON1 RDY MON2 RDY DS1874 Lower Memory, Register 6Fh: UPDATE MON3 RDY MON4 RDY BIT 7 BITS 7:2 RESERVED RSSIR BIT 0 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified.
PAGE 42
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 70h: ALARM3 70h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI BIT 7 42 MON2 LO BIT 0 BIT 7 TEMP HI: High-alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low-alarm status for temperature measurement.
PAGE 43
SFP+ Controller with Digital LDD Interface 71h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile MON3 HI MON3 LO MON4 HI DS1874 Lower Memory, Register 71h: ALARM2 MON4 LO RESERVED RESERVED RESERVED BIT 7 BIT 0 BIT 7 MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.
PAGE 44
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 72h: ALARM1 72h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO BIT 7 BITS 7:4 BIT 0 RESERVED BIT 3 HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting.
PAGE 45
SFP+ Controller with Digital LDD Interface 74h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI DS1874 Lower Memory, Register 74h: WARN3 VCC LO MON1 HI MON1 LO BIT 7 MON2 HI MON2 LO BIT 0 BIT 7 TEMP HI: High-warning status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low-warning status for temperature measurement.
PAGE 46
DS1874 SFP+ Controller with Digital LDD Interface Lower Memory, Register 75h: WARN2 75h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED BIT 7 BIT 0 BIT 7 MON3 HI: High-warning status for MON3 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 MON3 LO: Low-warning status for MON3 measurement.
PAGE 47
SFP+ Controller with Digital LDD Interface POWER-ON VALUE FFFF FFFFh READ ACCESS N/A WRITE ACCESS All MEMORY TYPE Volatile DS1874 Lower Memory, Register 7Bh–7Eh: Password Entry (PWE) 7Bh 231 230 229 228 227 226 225 224 7Ch 223 222 221 220 219 218 217 216 7Dh 215 214 213 212 211 210 29 28 7Eh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 There are two passwords for the DS1874. Each password is 4 bytes long.
PAGE 48
DS1874 SFP+ Controller with Digital LDD Interface Table 01h Register Descriptions Table 01h, Register 80h–BFh: EEPROM 80h–BFh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) WRITE ACCESS PW2 or (PW1 and RWTBL1A) MEMORY TYPE Nonvolatile (EE) EE EE EE EE EE EE EE BIT 7 EE BIT 0 EEPROM for PW1 and/or PW2 level access.
PAGE 49
SFP+ Controller with Digital LDD Interface F8h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) TEMP HI TEMP LO VCC HI VCC LO BIT 7 MON1 HI MON1 LO DS1874 Table 01h, Register F8h: ALARM EN3 MON2 HI MON2 LO BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 50
DS1874 SFP+ Controller with Digital LDD Interface Table 01h, Register F9h: ALARM EN2 F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED BIT 7 RESERVED BIT 0 Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
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SFP+ Controller with Digital LDD Interface FAh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED BIT 7 HBAL RESERVED DS1874 Table 01h, Register FAh: ALARM EN1 TXP HI TXP LO BIT 0 Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see Figure 12) logic.
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DS1874 SFP+ Controller with Digital LDD Interface Table 01h, Register FBh: ALARM EN0 FBh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED BIT 7 RESERVED BIT 0 Layout is identical to ALARM1 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or 05h.
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SFP+ Controller with Digital LDD Interface F8h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) TEMP HI TEMP LO VCC HI VCC LO MON1 HI BIT 7 MON1 LO DS1874 Table 01h, Register FCh: WARN EN3 MON2 HI MON2 LO BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
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DS1874 SFP+ Controller with Digital LDD Interface Table 01h, Register FDh: WARN EN2 F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED BIT 7 RESERVED BIT 0 Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
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SFP+ Controller with Digital LDD Interface Table 02h, Register 80h: MODE 80h POWER-ON VALUE 3Fh READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RTBL246) MEMORY TYPE Volatile SEEB RESERVED BIT 7 DAC1 EN DAC2 EN AEN MOD EN APC EN BIAS EN BIT 0 BIT 7 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register 81h: Temperature Index (TINDEX) 81h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h, 06h–08h.
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SFP+ Controller with Digital LDD Interface FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS (PW2 and DAC1 EN = 0) or (PW1 and RWTBL246 and DAC1 EN = 0) MEMORY TYPE Volatile DS1874 Table 02h, Register 84h–85h: DAC1 VALUE 84h 0 0 0 0 0 0 0 28 85h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for DAC1 and recalled from Table 07h at the adjusted memory address found in TINDEX.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register 88h: SAMPLE RATE 88h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) SEE SEE SEE SEE SEE APC_SR2 APC_SR1 BIT 7 BITS 7:3 APC_SR0 BIT 0 SEE APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample rate for comparison of APC control.
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SFP+ Controller with Digital LDD Interface DS1874 Table 02h, Register 89h: CNFGA 89h FACTORY DEFAULT 80h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) LOSC RESERVED INV LOS ASEL MASK INVRSOUT RESERVED BIT 7 RESERVED BIT 0 BIT 7 LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 13). 0 = LOS LO alarm is used as the source. 1 = (Default) LOS input pin is used as the source.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register 8Ah: CNFGB 8Ah FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) IN1C INVOUT1 RESERVED RESERVED RESERVED ALATCH QTLATCH BIT 7 60 BIT 0 BIT 7 IN1C: IN1 Software Control Bit (see Figure 13). 0 = IN1 pin’s logic controls OUT1 pin. 1 = OUT1 is active (bit 6 defines the polarity).
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SFP+ Controller with Digital LDD Interface 8Bh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED TXDM34 TXDFG TXDFLT TXDIO DS1874 Table 02h, Register 8Bh: CNFGC RSSI_FC BIT 7 BITS 7:6 RSSI_FF BIT 0 RESERVED BIT 5 TXDM34: Enables TXD to reset alarms and warnings associated to MON3 and MON4 during a TXD event.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register 8Dh: RESERVED FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) This register is reserved.
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SFP+ Controller with Digital LDD Interface FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) DS1874 Table 02h, Register 90h–91h: RESERVED These registers are reserved.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register A2h–A3h: VCC OFFSET Table 02h, Register A4h–A5h: MON1 OFFSET Table 02h, Register A6h–A7h: MON2 OFFSET Table 02h, Register A8h–A9h: MON3 FINE OFFSET Table 02h, Register AAh–ABh: MON4 OFFSET Table 02h, Register ACh–ADh: MON3 COARSE OFFSET A2h, A4h, A6h, A8h, AAh, ACh A3h, A5h, A7h, A9h, ABh, ADh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvola
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SFP+ Controller with Digital LDD Interface FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 or (PW1 and WPW1) MEMORY TYPE Nonvolatile (SEE) DS1874 Table 02h, Register B0h–B3h: PW1 B0h 231 230 229 228 227 226 225 224 B1h 223 222 221 220 219 218 217 216 B2h 215 214 213 212 211 210 29 28 B3h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The PWE value is compared against the value written to this location to enable PW1 access.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register B8h: LOS RANGING B8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED HLOS2 HLOS1 HLOS0 RESERVED LLOS2 LLOS21 BIT 7 LLOS0 BIT 0 This register controls the full-scale range of the quick-trip monitoring for the differential input’s of MON3. BIT 7 RESERVED (Default = 0) HLOS[2:0]: HLOS Full-Scale Ranging.
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SFP+ Controller with Digital LDD Interface FACTORY DEFAULT B9h 00h READ ACCESS PW2 WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) RESERVED DS1874 Table 02h, Register B9h: COMP RANGING BIAS2 BIAS1 BIAS0 RESERVED APC2 BIT 7 APC1 APC0 BIT 0 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register BAh: RESERVED FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) This register is reserved.
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SFP+ Controller with Digital LDD Interface BDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1874 Table 02h, Register BDh: LTXP 21 BIT 7 20 BIT 0 Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC DAC value recalled from Table 04h. If the difference is less than 0x00, 0x00 is used.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register C0h: PW_ENA C0h FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL78 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA BIT 7 70 WAUXB BIT 0 BIT 7 RWTBL78: Tables 07h–08h 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 6 RWTBL1C: Table 01h or 05h bytes F8h–FFh.
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SFP+ Controller with Digital LDD Interface C1h FACTORY DEFAULT 03h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 DS1874 Table 02h, Register C1h: PW_ENB WAUXAU WAUXBU BIT 7 BIT 0 BIT 7 RWTBL46: Read and Write Tables 04h, 06h 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register C2h: MODTI C2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The modulation temperature index defines the TempCo boundary for the MODULATION LUT. The MODTC bit (Table 02h, Register C6h) defines the polarity of the TempCo.
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SFP+ Controller with Digital LDD Interface C4h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 BIT 7 DS1874 Table 02h, Register C4h: DAC2TI 21 20 BIT 0 DAC2 temperature index defines the TempCo boundary for the DAC2 LUT. The DAC2TC bit (Table 02h, Register C6h) defines the polarity of the TempCo.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register C6h: LUTTC C6h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) MODTC DAC1TC DAC2TC RESERVED RESERVED RESERVED RESERVED BIT 7 BIT 0 BIT 7 MODTC: Modulation TempCo 0 = Negative TempCo.
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SFP+ Controller with Digital LDD Interface C7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 DS1874 Table 02h, Register C7h: TBLSELPON 22 21 BIT 7 20 BIT 0 Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register CBh–CCh: BIAS REGISTER FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE Volatile CBh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 28 CCh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for BIAS and resolved from the APC. This register is updated after each decision of the APC loop.
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SFP+ Controller with Digital LDD Interface FACTORY DEFAULT DEVICE VERSION READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE ROM CFh DS1874 Table 02h, Register CFh: DEVICE VER DEVICE VERSION BIT 7 BIT 0 Hardwired connections to show the device version.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register D8h–E7h: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE None These registers do not exist. Table 02h, Register E8h: RXCTRL1 E8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 MAX3798/MAX3799 register.
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SFP+ Controller with Digital LDD Interface EAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1874 Table 02h, Register EAh: SETCML 21 BIT 7 20 BIT 0 MAX3798/MAX3799 register.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register EDh: IMODMAX EDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 MAX3798/MAX3799 register.
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SFP+ Controller with Digital LDD Interface EFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1874 Table 02h, Register EFh: SETPWCTRL 21 BIT 7 20 BIT 0 MAX3798/MAX3799 register.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register F8h: 3WCTRL F8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 3WRW BIT 7 BITS 7:2 3WDIS BIT 0 RESERVED BIT 1 3WRW: Initiates a 3-wire write or read operation.
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SFP+ Controller with Digital LDD Interface FAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile 27 26 25 24 23 22 DS1874 Table 02h, Register FAh: WRITE 21 BIT 7 20 BIT 0 This byte is used during manual 3-wire communication. When a manual write is initiated, this register contains the data for the operation.
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DS1874 SFP+ Controller with Digital LDD Interface Table 02h, Register FDh: TXSTAT2 FDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 MAX3798/MAX3799 register. This value is read from the MAX3798/MAX3799 with the 3-wire interface every tRR (see the MAX3798/MAX3799 electrical characteristics).
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SFP+ Controller with Digital LDD Interface Table 06h, Register 80h–A3h: APC TE LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 BIT 7 21 20 BIT 0 The APC TE LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC.
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DS1874 SFP+ Controller with Digital LDD Interface Table 07h Register Descriptions Table 07h, Register 80h–A3h: DAC1 LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) and (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The DAC1 LUT is a set of registers assigned to hold the PWM profile for DAC1. The values in this table determine the set point for DAC1.
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SFP+ Controller with Digital LDD Interface Table 08h, Register 80h–A3h: DAC2 LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The DAC2 LUT is set of registers assigned to hold the PWM profile for DAC2. The values in this table determine the set point for DAC2.
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DS1874 SFP+ Controller with Digital LDD Interface Applications Information Power-Supply Decoupling To achieve best results, it is recommended that the power supply is decoupled with a 0.01µF or a 0.1µF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance. SDA and SCL Pullup Resistors SDA is an open-collector output on the DS1874 that requires a pullup resistor to realize high logic levels.