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General Description

The DS1870 is a dual-channel bias controller targeted

toward class AB LDMOS RF power-amplifier applica-

tions. It uses lookup tables (LUTs) to control 256-posi-

tion potentiometers based on the amplifier’s

temperature and drain voltage or current (or other

external monitored signal). With its internal temperature

sensor and multichannel A/D converter (ADC), the

DS1870 provides a cost-effective solution that improves

the amplifier’s efficiency by using nonlinear compensa-

tion schemes that are not possible with conventional

biasing solutions.

Applications

Cellular Base Stations

Medical Equipment

Industrial Controls

Optical Transceivers

Features

♦ Two-Channel Solution for Programmable RF Bias

Control

♦ The Potentiometer’s Position is Automatically

Updated to Compensate for the Ambient

Temperature and the Drain Voltage or Current

♦ A Five-Channel, 13-Bit ADC Continuously

Monitors the Ambient Temperature, V

, V

, I

D1,

and I

♦ Hi/Lo Alarms for Each ADC Channel can Trigger a

Fault Output

♦ Nonvolatile Memory for the Device Settings,

Lookup Tables, and 32-Bytes of User Memory

♦ I

C™-Compatible Serial Interface with Up to Eight

Devices on the Same Serial Bus

♦ Single 5V Power Supply

♦ Small 16-Pin TSSOP Package

♦ -40°C to +95°C Operational Temperature Range

DS1870

LDMOS RF Power-Amplifier Bias

Controller

______________________________________________ Maxim Integrated Products 1

TSSOP (173 mil)

16L

TOP VIEW

GND FAULT

SCL

SDA

COM

DS1870

Pin Configuration

Ordering Information

Rev 1; 5/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE

PIN-PACKAGE

DS1870E-010 -40°C to +95°C

16 TSSOP

(173 mil)

Typical Operating Circuit appears at end of data sheet.

C is a trademark of Philips Corp. Purchase of I

C compo-

nents of Maxim Integrated Products, Inc., or one of its subli-

censed Associated Companies, conveys a license under the

Philips I

C Patent Rights to use these components in an I

system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

Summary of content (28 pages)

PAGE 1
Rev 1; 5/04 LDMOS RF Power-Amplifier Bias Controller Features The DS1870 is a dual-channel bias controller targeted toward class AB LDMOS RF power-amplifier applications. It uses lookup tables (LUTs) to control 256-position potentiometers based on the amplifier’s temperature and drain voltage or current (or other external monitored signal).
PAGE 2
DS1870 LDMOS RF Power-Amplifier Bias Controller ABSOLUTE MAXIMUM RATINGS Operating Temperature Range ...........................-40°C to +95°C EEPROM Programming Temperature Range .........0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A Specification Voltage Range on VCC, HCOM, SDA, and SCL Pins Relative to Ground ...............................................................-0.
PAGE 3
LDMOS RF Power-Amplifier Bias Controller (VCC = +4.5 to 5.5V, TA = -40°C to +95°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VD Monitor FactoryCalibrated FS Code FFF8h 2.488 2.500 2.513 V VCC Monitor FactoryCalibrated FS Code FFF8h 6.521 6.553 6.587 V ID1 and ID2 Monitor FactoryCalibrated FS Code FFF8h 0.4975 0.5000 0.5025 V Resolution (VCC, VD, ID1, ID2) 0.0122 Accuracy (VCC, VD, ID1, ID2) 0.25 Update Rate for VCC, VD, ID1, ID2 tframe %FS 0.
PAGE 4
DS1870 LDMOS RF Power-Amplifier Bias Controller LOOKUP TABLE CHARACTERISTICS (VCC = +4.5 to 5.5V, TA = -40°C to +95°C.
PAGE 5
LDMOS RF Power-Amplifier Bias Controller (VCC = +4.5V to 5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 3) PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup Time SYMBOL fSCL CONDITIONS (Note 7) TYP MAX 400 UNITS kHz tBUF 1.3 µs tHD:STA 0.6 µs tLOW tHIGH 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 0.
PAGE 6
Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) 850 740 720 700 680 660 700 650 VCC = 5.0V 600 VCC = 4.5V 550 0.40 0.35 0.30 0.25 0.20 0.15 640 500 0.10 620 450 0.05 600 400 4.5 4.7 4.9 5.1 5.3 5.5 0 -40 -20 0 20 40 60 80 100 4.5 4.7 4.9 5.1 5.3 SUPPLY VOLTAGE (V) TEMPERATURE (°C) HCOM VOLTAGE (V) POTENTIOMETER 1 AND 2 OUTPUT VOLTAGE vs. POSITON POTENTIOMETER 1 DIFFERENTIAL NONLINEARITY vs.
PAGE 7
LDMOS RF Power-Amplifier Bias Controller 700 600 500 400 300 200 HCOM = 5.0V 100 800 700 600 500 400 300 200 HCOM = 5V WIPER VOLTAGE = 4V 100 0 0 1 2 3 5 4 200 DS1870 toc11 900 0 150 100 RPOT2 + RS2 50 0 RPOT1 + RS1 -50 -100 -150 -200 -40 -20 0 20 40 60 100 80 -40 -20 0 20 40 60 80 WIPER VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) POTENTIOMETER LOW TERMINAL VOLTAGE vs. TEMPERATURE VCC CONVERSION ERROR vs. SUPPLY VOLTAGE VD CONVERSION ERROR vs. INPUT VOLTAGE 0.
PAGE 8
LDMOS RF Power-Amplifier Bias Controller DS1870 Pin Description PIN 8 NAME FUNCTION 1 L1 Potentiometer 1 Low Terminal 2 W1 Potentiometer 1 Wiper Terminal 3 W2 Potentiometer 2 Wiper Terminal 4 L2 Potentiometer 2 Low Terminal 5 ID1 Drain Current 1 Monitor Input 6 ID2 Drain Current 2 Monitor Input 7 VD Drain Voltage Monitor Input 8 GND 9 FAULT 10 A0 11 A1 Ground Fault Output.
PAGE 9
LDMOS RF Power-Amplifier Bias Controller VCC ON-CHIP TEMP SENSOR VCC SDA SCL I2C INTERFACE CONTROL GAIN CALIBRATION REGISTERS OFFSET CALIBRATION REGISTERS A0 A1 + ∑ + 13-BIT ADC VCC MUX 32 BYTES USER MEMORY VD ID1 ADDRESS GENERATION ID2 A2 I2C DATA BUS VD ID1 VD ID2 INDEX LOAD POT1 DRAIN LUT TABLE 4 (64 BYTES) TEMP INDEX MEASURED VALUES FOR TEMP, VCC, VD, ID0, ID1 VD2 VD1 INDEX POT2 DRAIN LUT TABLE 5 (64 BYTES) LIMIT FLAG REGISTERS FAULT HI AND LO LIMITS FOR TEMP, VCC, VD, ID1, ID
PAGE 10
DS1870 LDMOS RF Power-Amplifier Bias Controller Table 1. Voltage-Monitor Factory Default Calibration Table 2. Voltage-Monitor Conversion Examples SIGNAL +FS SIGNAL +FS (hex) -FS SIGNAL -FS (hex) SIGNAL LSB WEIGHT (µV) VCC 6.553V FFF8 0V 0000 VCC 100.00 8080 3.29 VD 2.5V FFF8 0V 0000 VCC 100.00 C0F8 4.94 ID1 0.5V FFF8 0V 0000 VD 38.152 C000 1.875 ID2 0.5V FFF8 0V 0000 VD 38.152 8080 1.255 ID1 7.6303 8000 0.2500 ID2 7.6303 1328 0.
PAGE 11
LDMOS RF Power-Amplifier Bias Controller Table 4. Temperature Conversion Values MSB (bin) LSB (bin) 01000000 00000000 +64 01000000 00001111 +64.059 Temperature-Monitor Operation 01011111 00000000 +95 The internal temperature monitor values are stored as 16-bit 2’s complement numbers at memory addresses 60h to 61h. The round-robin update time (tframe) for the temperature register is the same as the voltage monitors.
PAGE 12
99h 9Ah DECREASING TEMPERATURE 98h 97h INCREASING TEMPERATURE 96h 95h 99h 9Ah DECREASING DRAIN VOLTAGE 98h 97h INCREASING DRAIN VOLTAGE 96h MEMORY LOCATION MEMORY LOCATION 9Ah MEMORY LOCATION DS1870 LDMOS RF Power-Amplifier Bias Controller 95h 2 4 6 8 10 TEMPERATURE (°C) 12 99h DECREASING DRAIN CURRENT 98h 97h 96h INCREASING DRAIN CURRENT 95h AA00 AC00 AEOO B000 B200 B400 DRAIN VOLTAGE CONVERSION (HEX) 2A00 2C00 2E00 3000 3200 3400 DRAIN CURRENT CONVERSION (HEX) Figure 1.
PAGE 13
LDMOS RF Power-Amplifier Bias Controller /* Assume that the null input is 0.5V */ /* Assume that the requirement for the LSB is 50µV */ FS = 65528 * 50e-6; /*3.2764V */ CNT1 = 0.5 / 50e-6; /* 1000 */ CNT2 = 0.9 X FS / 50e-6; /* 58981.5 */ /* So the null input is 0.5V and 90% of FS is 2.
PAGE 14
DS1870 LDMOS RF Power-Amplifier Bias Controller As the device powers up, the V CC LO alarm flag defaults to a 1 until the first V CC ADC conversion occurs and sets or clears the flag accordingly. The FAULT output is active when VCC < VPOA. Memory Description The DS1870 memory map is divided into six sections that include the lower memory (addresses 00h to 7Fh) and five memory tables (Figure 2).
PAGE 15
LDMOS RF Power-Amplifier Bias Controller WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 00 User Row0 User EE User EE User EE User EE User EE User EE User EE User EE 08 User Row1 User EE User EE User EE User EE User EE User EE User EE User EE 10 User Row2 User EE User EE User EE User EE User EE User EE User EE User EE 18 User Row3 User EE User EE User EE User EE User EE User EE User EE User EE 20 Threshold0
PAGE 16
DS1870 LDMOS RF Power-Amplifier Bias Controller TABLE 1 ( CONFIGURATION ) ROW (HEX) ROW NAME WORD 0 BYTE 0 WORD 1 BYTE 1 BYTE 2 WORD 2 BYTE 3 BYTE 4 WORD 3 BYTE 5 BYTE 6 BYTE 7 LUT Sel Fault Ena Reserved 80 Config Password 88 Scale0 Reserved Vcc Scale VD Scale ID1 Scale 90 Scale1 ID2 Scale Reserved Reserved Reserved 98 Offset0 Reserved Vcc Offset VD Offset ID1 offset A0 Offset1 ID2 Offset Reserved Reserved Temp Offset A8 LUT Index T Index O1 Index O2 Index BI
PAGE 17
LDMOS RF Power-Amplifier Bias Controller WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 80 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 88 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 90 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 98 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 A0 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 A8 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 B0 LUT POT
PAGE 18
DS1870 LDMOS RF Power-Amplifier Bias Controller WORD 0 BYTE 0 BYTE 1 POT2 POT2 TABLE 3 ( POT2 TEMP LUT) WORD 1 WORD 2 BYTE 2 BYTE 3 BYTE 4 BYTE 5 POT2 POT2 POT2 POT2 WORD 3 BYTE 6 BYTE 7 POT2 POT2 ROW (HEX) ROW NAME 80 LUT 88 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 90 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 98 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 A0 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 A8 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 PO
PAGE 19
LDMOS RF Power-Amplifier Bias Controller WORD 3 BYTE 6 BYTE 7 POT1 Off POT1 Off 80 LUT 88 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off 90 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off ROW NAME 98 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off A0 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off A8 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Of
PAGE 20
DS1870 LDMOS RF Power-Amplifier Bias Controller Register Description The register descriptions are organized by the register’s row address starting with the lower memory, then proceeding through each lookup table in order. The format of the register description is shown below.
PAGE 21
LDMOS RF Power-Amplifier Bias Controller A2D Value1 ID2 Value Status Hi Alarm <0000h> The signed 2’s complement direct-to-temperature measurement. <0000h> Unsigned VCC voltage measurement. <0000h> Unsigned VD voltage measurement. <0000h> Unsigned ID1 voltage measurement. <0000h> Unsigned ID2 voltage measurement. <00h> High-Alarm Status bits. a) Temp Hi b) Vcc Hi High-alarm status for temperature measurement. High-alarm status for VCC measurement.
PAGE 22
DS1870 LDMOS RF Power-Amplifier Bias Controller PWE PWE Password Entry. Until the correct password is written to this location, the only memory that can be written are addresses 78h to 7Fh. This includes the PWE and Table_Select locations. All memory is readable regardless of the PWE value. TBL Sel <00h> Table Select. The DS1870 contains four tables (1 to 5). Writing a (1 to 5) value to this register grants access to the corresponding table.
PAGE 23
LDMOS RF Power-Amplifier Bias Controller O1 Index <00h> Holds the calculated index based on the temperature measurement. This index is used to address LUTs 2 and 3. <00h> Holds the calculated index based on the VD or ID1 measurement (dependant on ‘LUT Sel’ byte). This index is used to address LUT 4. O2 Index <00h> Holds the calculated index based on the VD or ID2 measurement (dependant on ‘LUT Sel’ byte). This index is used to address LUT 5.
PAGE 24
DS1870 LDMOS RF Power-Amplifier Bias Controller TABLE 2 (TEMP LUT FOR POT 1) Bytes 80h–C7h POT1 <00h>The unsigned base value for POT1. TABLE 3 (TEMP LUT FOR POT 2) Bytes 80h–C7h POT2 <00h>The unsigned base value for POT2. TABLE 4 (DRAIN LUT FOR POT 1) Bytes 80h–B8h POT1 Off <00h>The signed 2’s complement offset value for POT1. TABLE 5 (DRAIN LUT FOR POT 2) Bytes 80h–B8h POT2 Off <00h>The signed 2’s complement offset value for POT2.
PAGE 25
LDMOS RF Power-Amplifier Bias Controller 1 MOST SIGNIFICANT BIT 0 1 0 A2 A1 A0 R/W A2, A1, AND A0 PIN VALUES DETERMINES READ OR WRITE Figure 4. Slave Address Byte setup and hold time requirements (Figure 3). Data is shifted into the device during the rising edge of the SCL. Bit read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 3) before the next rising edge of SCL during a bit read.
PAGE 26
DS1870 LDMOS RF Power-Amplifier Bias Controller dition, and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time an EEPROM page is written, the DS1870 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS1870 will not acknowledge its slave address because it is busy.
PAGE 27
LDMOS RF Power-Amplifier Bias Controller 5V 4.7kΩ 3 PLACES 28V VCC FAULT 49.9kΩ DS1870 SDA FACTORY-CALIBRATED 13-BIT ADC (CUSTOMER ADJUSTABLE FULLSCALE AND OFFSET VALUES) SCL 4.22kΩ A2 A1 VD A0 N.C. N.C. ID2 N.C. W1 RPOT1 RS1 L1 RS2 L2 W2 GND HCOM RPOT2 ID1 N.C. MAX6165B 5V REFERENCE RF POWER AMP RFIN RFOUT NOTES: 1) IN THIS CONFIGURATION, THE VOLTAGE RANGE OF W1 AND W2 IS 3V-5V. THIS RANGE CAN BE EXTENDED USING EXTERNAL RESISTORS.
PAGE 28
SDA and SCL Pullup Resistors Advanced Application SDA is an open-collector output on the DS1870 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC electrical characteristics are within specification.