Manual

DS1841
Temperature-Controlled, NV, I
2
C,
Logarithmic Resistor
10 ______________________________________________________________________________________
Memory Description
The DS1841’s internal memory consists of both volatile
and NV registers that are organized into eight byte
rows. Three control registers as well as specialized
data registers are used to control the wiper and drive
the LUT.
Register 00h: Initial Value Register (IVR)
FACTORY DEFAULT (IVR) 00h
MEMORY TYPE NV
MEMORY TYPE Volatile
00h IVR
Bit 7 Bit 0
If SEE bit = 0, an I
2
C READ retrieves the IVR value and an I
2
C WRITE sets the wiper position in volatile memory and
updates IVR in NV memory with this new value. If SEE bit = 1, an I
2
C READ retrieves the WR value and an I
2
C WRITE
sets the wiper position (volatile) and the IVR value is not modified. During power-up, IVR’s value is used to set the wiper
position.
Register 02h: Control Register 0 (CR0)
FACTORY DEFAULT 00h
MEMORY TYPE Volatile
02h SEE Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7 Bit 0
Bit 7
SEE Controls IVR and WR functionality, as well as the memory type for Control Register 1.
0 = (Default) Issuing an I
2
C READ of the value in address 00h retrieves the IVR value. Issuing an I
2
C
WRITE to address 00h sets both the wiper’s position (volatile) and the IVR value (nonvolatile) to the
same value. Writes to Control Register 1 (03h) are stored in shadowed SRAM and EEPROM.
1 = Issuing an I
2
C READ of the value in address 00h retrieves the WR value. Issuing an I
2
C WRITE to
address 00h only sets the wiper’s position (volatile). The IVR value is not modified. Writes to Control
Register 1 (03h) are stored in shadowed SRAM only.
Bits 6 to 0 Reserved.
Control Register 0 determines how the wiper position values (volatile and NV versions) are set, as well as how writes to
Control Register 1 are stored.
The IVR is located at memory address 00h and is implemented as EEPROM shadowed SRAM. This register can be
visualized as an SRAM byte (the WR portion) in parallel with an EEPROM byte (the IVR portion). The operation of the
register is controlled by the Shadow EEPROM (SEE) bit in Control Register 0, address 02h, bit 7. When the SEE bit = 0
(default), data written to memory address 00h by I
2
C actually gets stored in both SRAM (WR) and EEPROM (IVR). When
SEE = 1, only the SRAM (WR) is written to the new value. The EEPROM byte (IVR) continues to store the last value
written to it when SEE was 0. Reading memory address 00h reads the value stored in WR. The SEE bit is volatile and its
power-up default state is 0.
Register Descriptions