Owner's manual

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FEATURES

§ Real-time clock (RTC) counts seconds,

minutes, hours, date of the month, month,

day of the week, and year with leap-year

compensation valid up to 2100

§ 96-byte, battery-backed NV RAM for data

storage

§ Two time-of-day alarms, programmable on

combination of seconds, minutes, hours, and

day of the week

§ Serial interface supports Motorola SPI

™

(serial peripheral interface) serial data ports

or standard 3-wire interface

§ Burst mode for reading/writing successive

addresses in clock/RAM

§ Dual-power supply pins for primary and

backup power supplies

§ Optional trickle charge output to backup

supply

§ 2.0V to 5.5V operation

§ Optional industrial temperature range:

-40°C to +85°C

§ Available in space-efficient, 20-pin TSSOP

package

§ Underwriters Laboratory (UL) recognized

ORDERING INFORMATION

DS1305 16-Pin DIP (300mil)

DS1305N 16-Pin DIP (Industrial)

DS1305E 20-Pin TSSOP (173mil)

DS1305EN 20-Pin TSSOP (Industrial)

PIN ASSIGNMENT

CC2

120V

CC1

BAT

219NC

X1 3 18 PF

NC 4 17 V

CCIF

X2 5 16 SD0

NC 6 15 SDI

INT0 7 14 SCLK

NC 8 13 NC

INT1 9 12 CE

GND 10 11 SERMODE

DS1305 20-Pin TSSOP (4.4mm)

CC2

1 16 V

CC1

BAT

215PF

X1 3 14 V

CCIF

X2 4 13 SDO

NC 5 12 SDI

INT0 6 11 SCLK

INT1 7 10 CE

GND 8 9 SERMODE

DS1305 16-Pin DIP (300mil)

TYPICAL OPERATING CIRCUIT

www.maxim-ic.com

DS1305

Serial Alarm Real-Time Clock

Package dimension information can be found at:

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

SPI is a trademark of Motorola, Inc.

Summary of content (20 pages)

PAGE 1
DS1305 Serial Alarm Real-Time Clock www.maxim-ic.
PAGE 2
DS1305 PIN DESCRIPTION VCC1 VCC2 VBAT VCCIF GND X1, X2 - Primary Power Supply - Backup Power Supply - +3V Battery Input - Interface Logic Power-Supply Input - Ground - 32,768kHz Crystal Connection INT0 - Interrupt 0 Output INT1 - Interrupt 1 Output SDI - Serial Data In SDO - Serial Data Out CE - Chip Enable SCLK - Serial Clock SERMODE - Serial Interface Mode PF - Power-Fail Output DESCRIPTION The DS1305 serial alarm real-time clock provides a full binary coded decimal (BCD) clock calendar that is accesse
PAGE 3
DS1305 OPERATION The block diagram in Figure 1 shows the main elements of the serial alarm RTC. The following paragraphs describe the function of each pin. Figure 1. BLOCK DIAGRAM OSCILLATOR AND COUNTDOWN CHAIN 1Hz SIGNAL DESCRIPTIONS VCC1 – DC power is provided to the device on this pin. VCC1 is the primary power supply. VCC2 – This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy source is connected to this pin.
PAGE 4
DS1305 SDI (Serial Data Input) – When SPI communication is selected, the SDI pin is the serial data input for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and SDO pins function as a single I/O pin when tied together). SDO (Serial Data Output) – When SPI communication is selected, the SDO pin is the serial data output for the SPI bus.
PAGE 5
DS1305 RECOMMENDED LAYOUT FOR CRYSTAL CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast.
PAGE 6
DS1305 Figure 2.
PAGE 7
DS1305 During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated. Table 1.
PAGE 8
DS1305 STATUS REGISTER (READ 10H) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0 0 0 0 0 0 IRQF1 IRQF0 IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin goes low. IRQF0 is cleared when the address pointer goes to any of the Alarm 0 registers during a read or write.
PAGE 9
DS1305 Table 2.
PAGE 10
DS1305 Figure 4. POWER SUPPLY CONFIGURATIONS Configuration 1: Backup Supply is a Nonrechargeable Lithium Battery VCCTP Note: Device is write-protected if VCC < VCCTP. Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor Note: Device does not provide automatic write protection.
PAGE 11
DS1305 SERIAL INTERFACE The DS1305 offers the flexibility to choose between two serial interface modes. The DS1305 can communicate with the SPI interface or with a standard 3-wire interface. The interface method used is determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected. When this pin is connected to ground, standard 3-wire communication is selected.
PAGE 12
DS1305 Figure 5. SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER CLOCK POLARITY (CPOL) CE CPOL = 1 SCLK SHIFT DATA OUT (READ) DATA LATCH (WRITE) SHIFT DATA OUT (READ) DATA LATCH (WRITE) CPOL = 0 SCLK 1) CPHA bit polarity (if applicable) may need to be set accordingly. 2) CPOL is a bit that is set in the microcontroller’s control register. 3) SDO remains at high-Z until 8 bits of data are ready to be shifted out during a read.
PAGE 13
DS1305 The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of this byte determines if a read or write takes place. If A7 is 0, one or more read cycles occur. If A7 is 1, one or more write cycles occur. Data transfers can occur one byte at a time or in multiple-byte burst mode. After CE is driven high an address is written to the DS1305. After the address, one or more data bytes can be written or read.
PAGE 14
DS1305 3-WIRE INTERFACE The 3-wire interface mode operates similarly to the SPI mode. However, in 3-wire mode there is one I/O instead of separate data in and data out signals. The 3-wire interface consists of the I/O (SDI and SDO pins tied together), CE, and SCLK pins. In 3-wire mode, each byte is shifted in LSB first unlike SPI mode where each byte is shifted in MSB first. As is the case with the SPI mode, an address byte is written to the device followed by a single data byte or multiple data bytes.
PAGE 15
DS1305 ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Storage Temperature Range Soldering Temperature Range -0.5V to +7.0V -55°C to +125°C See IPC/JEDEC J-STD-020A *This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
PAGE 16
DS1305 DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Output Leakage Logic 0 Output IOL= 1.5mA IOL = 4.0mA Logic 1 Output IOH = -0.4mA IOH = -1.
PAGE 17
DS1305 3-WIRE AC ELECTRICAL CHARACTERISTICS PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall CE to CLK Setup CLK to CE Hold CE Inactive Time CE to Output High-Z SCLK to Output High-Z SYMBOL VCC = 2.0V tDC VCC = 5V VCC = 2.0V tCDH VCC = 5V VCC = 2.0V tCDD VCC = 5V VCC = 2.0V tCL VCC = 5V VCC = 2.0V tCH VCC = 5V VCC = 2.0V tCLK VCC = 5V VCC = 2.0V tR, tF VCC = 5V VCC = 2.0V tCC VCC = 5V VCC = 2.0V tCCH VCC = 5V VCC = 2.
PAGE 18
DS1305 Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER SPI AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Data to CLK Setup tDC CLK to Data Hold tCDH CLK to Data Delay tCDD CLK Low Time tCL CLK High Time tCH CLK Frequency tCLK CLK Rise and Fall tR, tF CE to CLK Setup tCC CLK to CE Hold tCCH CE Inactive Time tCWH CE to Output High-Z tCDZ MIN VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.
PAGE 19
DS1305 Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER Figure 13.
PAGE 20
DS1305 NOTES: 1) ICC1T and ICC2T are specified with CE set to a logic 0 and EOSC bit = 0 (oscillator enabled). 2) ICC1A and ICC2A are specified with CE = VCC, SCLK=2MHz at VCC = 5V; SCLK = 500kHz at VCC = 2.0V, VIL = 0V, VIH = VCC, and EOSC bit = 0 (oscillator enabled). 3) Measured at VIH = 2.0V or VIL = 0.8V and 10ms maximum rise and fall time. 4) Measured with 50pF load. 5) Measured at VOH = 2.4V or VOL = 0.4V. 6) ICC1S and ICC2S are specified with CE set to a logic 0.