User guide

DS1254
10 of 17
Figure 4. MEMORY READ CYCLE TIMING (Note 9)
Figure 5. MEMORY WRITE CYCLE TIMING, WRITE ENABLE CONTROLLED
(Notes 5, 6, 8, 10, 11, 12, and 13)
t
RC
ADDRESS
t
ACC
CE
OE
DQ0–DQ7
t
OH
t
CO
t
OE
t
COE
t
COE
t
OD
t
OD
OUTPUT
DATA VALID
t
WC
t
AH1
t
AW
t
OEW
t
DS
DATA IN
STABLE
t
DH1
t
ODW
t
WP
ADDRESS
CE
WE
DQ0–DQ7