DS1689/DS1693 3-Volt/5-Volt Serialized Real-Time Clock with NV RAM Control www.maxim-ic.
DS1689/DS1693 DESCRIPTION The DS1689/DS1693 is a real time clock (RTC) designed as a successor to the industry standard DS1285, DS1385, DS1485, and DS1585 PC real time clocks. This device provides the industry standard DS1285 clock function with the new feature of either +3.0- or +5.0 volt operation and automatic backup and write protection to an external SRAM.
DS1689/DS1693 VCCO (External SRAM Power Supply Output) - This pin will be internally connected to VCCI when VCCI is within nominal limits. However, during power fail, VCCO will be internally connected to the VBAT or VBAUX (whichever is larger). For 5-volt operation, switch over from VCCI to the backup supply occurs when VCCI drops below the larger of VBAT and VBAUX. For 3-volt operation, switch over from VCCI to the backup supply occurs at VPF if VPF is less than VBAT and VBAUX.
DS1689/DS1693 AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus change from address to data occurs during the internal RAM access time.
DS1689/DS1693 (Kickstart Input; active low) - When VCC is removed from the DS1689/DS1693, the system can be powered on in response to an active low transition on the KS pin, as might be generated from a key closure. VBAUX must be present and Auxiliary Battery Enable bit (ABE) must be set to 1 if the kickstart function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin can be used as an interrupt input.
DS1689/DS1693 When 5-volt operation is selected, the device is fully accessible and data can be written and read only when VCCI is greater than 4.5 volts. When VCCI is below 4.5 volts, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater of VBAT and VBAUX, the RAM and timekeeper are switched over to a lithium battery connected either to the VBAT pin or VBAUX pin.
DS1689/DS1693 TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format.
DS1689/DS1693 TIME, CALENDAR AND ALARM DATA MODES Table 1 ADDRESS LOCATION FUNCTION 00H 01H 02H 03H 04H Seconds Seconds Alarm Minutes Minutes Alarm Hours 12-hr Mode Hours 24-hr Mode 05H Hours Alarm 12-hr Mode Hours Alarm 24-hr Mode 06H Day of Week Sunday=1 07H Date of Month 08H Month 09H Year BANK1, 48H Century BANK 1, 49H Date Alarm DECIMAL RANGE 0-59 0-59 0-59 0-59 1-12 0-23 1-12 RANGE BINARY DATA BCD DATA MODE MODE 00-3B 00-59 00-3B 00-59 00-3B 00-59 00-3B 00-59 01-0C AM, 81-8C PM 01-12 AM, 81-92 P
DS1689/DS1693 The application software can select which interrupts, if any are to be used. There are a total of 6 bits including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The extended register locations are described later. Writing a logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ . pin from being asserted from that interrupt condition.
DS1689/DS1693 A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as it was in the DS1287.
DS1689/DS1693 PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 2 EXT. REG. B SELECT BITS REGISTER A tPI PERIODIC INTERRUPT RATE E32K RS3 RS2 RS1 RS0 0 0 0 0 0 None 0 0 0 0 1 3.90625 ms 0 0 0 1 0 7.8125 ms 0 0 0 1 1 122.070 ms 0 0 1 0 0 244.141 ms 0 0 1 0 1 488.281 ms 0 0 1 1 0 976.5625 ms 0 0 1 1 1 1.953125 ms 0 1 0 0 0 3.90625 ms 0 1 0 0 1 7.8125 ms 0 1 0 1 0 15.625 ms 0 1 0 1 1 31.25 ms 0 1 1 0 0 62.
DS1689/DS1693 REGISTER A MSB BIT 7 UIP BIT 6 DV2 BIT 5 DV1 BIT 4 DV0 BIT 3 RS3 BIT 2 RS2 BIT 1 RS1 LSB BIT 0 RS0 UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 ms. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only.
DS1689/DS1693 REGISTER B MSB BIT 7 SET BIT 6 PIE BIT 5 AIE BIT 4 UIE BIT 3 SQWE BIT 2 DM BIT 1 24/12 LSB BIT 0 DSE SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner.
DS1689/DS1693 REGISTER C MSB BIT 7 IRQF BIT 6 PF BIT 5 AF BIT 4 UF BIT 3 0 BIT 2 0 BIT 1 0 LSB BIT 0 0 IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 WF = WIE = 1 KF = KSE = 1 RF = RIE = 1 i.e., IRQF = (PF · PIE) + (AF · AIE) + (UF · UIE) + (WF · WIE) + (KF · KSE) + (RF · RIE) Any time the IRQF bit is a one, the IRQ pin is driven low.
DS1689/DS1693 EXTENDED FUNCTIONS The extended functions provided by the DS1689/DS1693 that are new to the RAMified RTC family are accessed via a software controlled bank switching scheme, as illustrated in Figure 4. In bank 0, the clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As a result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS1689/DS1693 clock registers with no changes.
DS1689/DS1693 DS1689/DS1693 EXTENDED REGISTER BANK DEFINITION Figure 4 16 of 32
DS1689/DS1693 SILICON SERIAL NUMBER/CUSTOMER SPECIFIC ROM A total of 128 bits are available for use as serial number/ROM. These bits may be used as a 128-bit serial number or as a unique 64-bit serial number and 64-bit customer specific serial number or ROM. The unique 64-bit serial number is located in bank 1 registers 40H-47H. This serial number is divided into three parts. The first byte in register 40H contains a model number to identify the device type and revision of the DS1689/DS1693.
DS1689/DS1693 Similarly, the kickstart feature is controlled through the Kickstart Interrupt Enable bit in extended control register B (KSE, bank 1, 04BH). A wake-up sequence will occur as follows: When wake-up is enabled via WIE = 1 while the system is powered down (no VCC voltage), the clock/calendar will monitor the current date for a match condition with the date alarm register (bank 1, register 049H).
DS1689/DS1693 addition, the other possible interrupt sources within the DS1689/DS1693 may cause IRQ to be driven low. While system power is applied, the on chip logic will always attempt to drive the PWR pin active in response to the enabled kickstart or wake-up condition. This is true even if PWR was previously inactive as the result of power being applied by some means other than wake-up or kickstart. The system may be powered down under software control by setting the PAB bit to a logic 1.
DS1689/DS1693 VRT2 - This status bit gives the condition of the auxiliary battery. It is set to a logic 1 condition when the external lithium battery is connected to the VBAUX. If this bit is read as a logic 0, the external battery should be replaced. INCR - Increment in Progress status bit. This bit is set to a 1 when an increment to the time/date registers is in progress and the alarm checks are being made.
DS1689/DS1693 and PWR will be driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF bit will have no effect on the PWR or IRQ pins. IRQ KSE - Kickstart Interrupt Enable. When VCC voltage is absent and KSE is set to a 1, the PWR pin will be driven active low when a kickstart condition occurs ( KS pulsed low), causing the KF bit to be set to 1. When VCC is then applied, the IRQ pin will also be driven low.
DS1689/DS1693 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Storage Temperature Soldering Temperature -0.3V to +7.0V -40°C to +70°C 260°C for 10 seconds (See Note 18) See IPC/JEDEC Standard J-STD-020A for surface mount devices *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS1689/DS1693 DC ELECTRICAL CHARACTERISTICS Over the operating range (5V) PARAMETER Average VCC Power Supply Current CMOS Standby Current ( CS =VCC-0.2V) Input Leakage Current (any input) Input Leakage PSEL Input Leakage Output Leakage Current Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = +2.
DS1689/DS1693 DC ELECTRICAL CHARACTERISTICS Over the operating range (3V) PARAMETER Average VCC Power Supply Current CMOS Standby Current ( CS =VCC-0.2V) Input Leakage Current (any input) Input Leakage PSEL Input Leakage Output Leakage Current Output Logic 1 Voltage (IOUT = 0.4 mA) Output Logic 0 Voltage (IOUT = 0.
DS1689/DS1693 DS1689/DS1693 BUS TIMING FOR READ CYCLE TO RTC RTC AC TIMING CHARACTERISTICS Over the operating range (5V) PARAMETER Cycle Time Pulse Width, RD / WR Low Pulse Width, RD / WR High Input Rise and Fall Time Chip Select Setup Time Before WR , or RD Chip Select Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid Time to ALE Fall Muxed Address Hold Time from ALE Fall RD or WR High Setup to ALE Rise Pulse Width ALE High ALE Low Setup to RD or WR Fall Output Data Delay Time from R
DS1689/DS1693 DS1689/DS1693 BUS TIMING FOR WRITE CYCLE TO RTC AND RTC REGISTERS POWER-UP CONDITION 3-VOLT OPERATION 26 of 32
DS1689/DS1693 POWER-DOWN CONDITION 3-VOLT OPERATION POWER-UP CONDITION 5.0-VOLT OPERATION POWER-DOWN CONDITION 5.
DS1689/DS1693 POWER-UP POWER-DOWN TIMING 5-VOLT OPERATION PARAMETER CS High to Power-Fail Recovery at Power-up VCC Slew Rate Power-down VCC Slew Rate Power-down VCC Slew Rate Power-up Expected Data Retention SYMBOL tPF tREC tF 4.0 £ VCC £ 4.5V tFB 3.0 £ VCC £ 4.0V tR 4.5V ³ VCC ³ 4.
DS1689/DS1693 WAKE-UP/KICKSTART TIMING NOTE: Time intervals shown above are referenced in Wake-up/Kickstart section. * This condition can occur when the device is operated in 3-volt mode.
DS1689/DS1693 NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25°C and nominal supplies. 3. Outputs are open. 4. Value for voltage and currents is from the VCCI input pin to the VCCO pin. 5. Write protection trip point occurs during power fail prior to switchover from VCC to VBAT. 6. Value for voltage and currents is from the VBAT input pin to the VCCO pin. 7. Applies to the AD0-AD7 pins, and the SQW pin when each is in a high impedance state. 8. The IRQ pin is open drain. 9.
DS1689/DS1693 DS1689S 28-PIN SOIC PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 31 of 32 28-PIN MIN MAX 0.697 0.728 17.70 18.50 0.324 0.350 8.23 8.90 0.087 0.118 2.20 3.00 0.016 0.050 0.40 1.27 0.002 0.014 0.05 0.35 0.100 0.120 2.55 3.05 0.050 BSC 1.27 BSC 0.453 0.500 11.50 12.70 0.006 0.013 0.14 0.32 0.014 0.020 0.35 0.
DS1689/DS1693 DS1693 28-PIN 740-MIL MODULE PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM NOTE: 32 of 32 28-PIN MIN MAX 1.520 1.540 38.61 39.12 0.695 0.740 17.65 18.80 0.350 0.375 8.89 9.52 0.100 0.130 2.54 3.30 0.015 0.030 0.38 0.76 0.110 0.140 2.79 3.56 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.008 0.012 0.20 0.30 0.015 0.021 0.38 0.53 PINS 2, 3, 19 AND 23 ARE MISSING BY DESIGN.
