User Manual

Functional Description (Continued)
The standard control bus signals of the 8080 CS
,RDand
WR
) can be directly wired to the digital control inputs of the
A/D and the bus timing requirements are met to allow both
starting the converter and outputting the data onto the data
bus. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100 pF.
4.1.1 Sample 8080A CPU Interfacing Circuitry and
Program
The following sample program and associated hardware
shown in
Figure 10 may be used to input data from the
converter to the INS8080A CPU chip set (comprised of the
INS8080A microprocessor, the INS8228 system controller
and the INS8224 clock generator). For simplicity, the A/D is
controlled as an I/O device, specifically an 8-bit bi-direction-
al port located at an arbitrarily chosen port address, E0. The
TRI-STATE output capability of the A/D eliminates the need
for a peripheral interface device, however address decoding
is still required to generate the appropriate CS
for the con-
verter.
It is important to note that in systems where the A/D con-
verter is 1-of-8 or less I/O mapped devices, no address
decoding circuitry is necessary. Each of the 8 address bits
(A0 to A7) can be directly used as CS
inputsÐone for each
I/O device.
4.1.2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series
(see
Figure 11 ) is simpler than the 8080A CPU interface.
There are 24 I/O lines and three test input lines in the 8048.
With these extra I/O lines available, one of the I/O lines (bit
0 of port 1) is used as the chip select signal to the A/D, thus
eliminating the use of an external address decoder. Bus
control signals RD
,WRand INT of the 8048 are tied directly
to the A/D. The 16 converted data words are stored at on-
chip RAM locations from 20 to 2F (Hex). The RD
and WR
signals are generated by reading from and writing into a
dummy address, respectively. A sample interface program
is shown below.
TL/H/5671–21
FIGURE 11. INS8048 Interface
SAMPLE PROGRAM FOR
FIGURE 11 INS8048 INTERFACE
04 10 JMP 10H : Program starts at addr 10
ORG 3H
04 50 JMP 50H ; Interrupt jump vector
ORG 10H ; Main program
99 FE ANL P1, #0FEH ; Chip select
81 MOVX A, @R1 ; Read in the 1st data
; to reset the intr
89 01 START: ORL P1,
Ý
1 ; Set port pin high
B8 20 MOV R0, #20H ; Data address
B9 FF MOV R1, #0FFH ; Dummy address
BA 10 MOV R2, #10H ; Counter for 16 bytes
23 FF AGAIN: MOV A, #0FFH ; Set ACC for intr loop
99 FE ANL P1, #0FEH ; Send CS (bit 0 of P1)
91 MOVX @R1, A ; Send WR out
05 EN I ; Enable interrupt
96 21 LOOP: JNZ LOOP ; Wait for interrupt
EA 1B DJNZ R2, AGAIN ; If 16 bytes are read
00 NOP ; go to user’s program
00 NOP
ORG 50H
81 INDATA: MOVX A, @R1 ; Input data, CS still low
A0 MOV @R0, A ; Store in memory
18 INC R0 ; Increment storage counter
89 01 ORL P1, #1 ; Reset CS signal
27 CLR A ; Clear ACC to get out of
93 RETR ; the interrupt loop
22