User guide

BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
6/25
z
Synchronous data timing
t BUF
t PD
t HIGH
t HD : STA t LOW
t F t R
SCL
START BIT STOP BIT
SCL
SDA
t DH
t SU : DAT t HD : DAT
t SU : STOt HD : STAt SU : STA
SDA
(OUT)
SDA
(IN)
Fig.4 SYNCHRONOUS DATA TIMING
•
SDA data is latched into the chip at the rising edge of SCL clock.
•
Output data toggles at the falling edge of SCL clock.
z
Write cycle timing
ACKD0
t WR
SDA
SCL
START CONDITIONSTOP CONDITION
WRITE DATA (n)
Fig.5 WRITE CYCLE TIMING