Manual

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
Memory ICs
!
!!
!Timing charts
SYNCHRONOUS DATA TIMING
t BUF
t PD
t HIGH
t HD : STA t LOW
t F t R
SCL
START BIT STOP BIT
SCL
SDA
t SU : DAT t HD : DAT
t SU : STOt HD : STAt SU : STA
SDA
(OUT)
SDA
(IN)
Fig.7
•SDA data is latched into the chip at the rising edge of the SCL clock.
•Output data toggles at the falling edge of the SCL clock.
WRITE CYCLE TIMING
ACKD0
(n)
tWR
SDA
SCL
START CONDITIONSTOP CONDITION
WRITE DATA
Fig.8
WRITE ENABLE TIMING
Fig.9
SDA
t
VSU tVHD
WRITE COMMAND
VCLK
SCL
START BIT
STOP BIT