Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny261/461/861) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861) Endurance: 100,000 Write/Erase Cyc
1. Pin Configurations Figure 1-1.
ATtiny261/461/861 2. Overview The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram GND Figure 2-1. VCC 2.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny261/461/861 2.2.6 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
ATtiny261/461/861 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
5. AVR CPU Core 5.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 5-1.
ATtiny261/461/861 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
5.3.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
ATtiny261/461/861 5.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
Figure 5-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.
ATtiny261/461/861 5.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
ATtiny261/461/861 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 5.7.
6. AVR Memories This section describes the different memories in the ATtiny261/461/861. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny261/461/861 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 6.1 In-System Re-programmable Flash Program Memory The ATtiny261/461/861 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage.
ATtiny261/461/861 When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny261/461/861 are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 11. Figure 6-2.
6.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 6-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down.
ATtiny261/461/861 The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in ”OSCCAL – Oscillator Calibration Register” on page 32. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATtiny261/461/861 6.4 I/O Memory The I/O space definition of the ATtiny261/461/861 is shown in ”Register Summary” on page 218. All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
6.5.2 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1D (0x3D) EEDR • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
ATtiny261/461/861 • Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.
7. System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 34. The clock systems are detailed below. Figure 7-1. Clock Distribution 7.1.
ATtiny261/461/861 7.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK The internal PLL in ATtiny261/461/861 generates a clock frequency that is 8x or 4x multiplied from a source input depending on the Low Speed Mode (LSM) bit. The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8.0 MHz. Thus the output of the PLL, the fast peripheral clock is 64 MHz or 32 MHz.
7.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Device Clocking Options Select(1) vs. PB4 and PB5 Functionality Table 7-1. Device Clocking Option CKSEL3..0 PB4 PB5 External Clock 0000 XTAL1 I/O PLL Clock 0001 I/O I/O Calibrated Internal RC Oscillator 8.
ATtiny261/461/861 Figure 7-3. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-3. Table 7-3. Start-up Times for the External Clock Selection SUT1..
7.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 23-1 on page 188 and ”Internal Oscillator Speed” on page 211 for more details. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 31 for more details.
ATtiny261/461/861 7.7 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “0011”. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-8. Table 7-8. Start-up Times for the 128 kHz Internal Oscillator SUT1..
Figure 7-4. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-10. Table 7-10. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1.
ATtiny261/461/861 Notes: 7.10 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
7.12 7.12.1 Register Description OSCCAL – Oscillator Calibration Register Bit 7 6 5 4 3 2 1 0 0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATtiny261/461/861 nous peripherals is reduced when a division factor is used. The division factors are given in Table 7-12. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
8. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 8.
ATtiny261/461/861 8.3 ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements.
8.7.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to ”ADC – Analog to Digital Converter” on page 142 for details on ADC operation. 8.7.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used.
ATtiny261/461/861 Refer to ”DIDR0 – Digital Input Disable Register 0” on page 160 or ”DIDR1 – Digital Input Disable Register 1” on page 160 for details. 8.8 8.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for power management.
• Bit 2- PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC.
ATtiny261/461/861 9. System Control and Reset 9.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 shows the reset logic.
9.0.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 189. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATtiny261/461/861 Figure 9-4. External Reset During Operation CC 9.0.5 Brown-out Detection ATtiny261/461/861 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Figure 9-6. Watchdog Reset During Operation CC CK 9.1 Internal Voltage Reference ATtiny261/461/861 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.1.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”System and Reset Characteristics” on page 189.
ATtiny261/461/861 Table 9-1. WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level WDTON WDT Initial State How to Disable the WDT How to Change Timeout Unprogrammed 1 Disabled Timed sequence No limitations Programmed 2 Enabled Always enabled Timed sequence Watchdog Timer OSC/512K OSC/1024K OSC/256K OSC/64K OSC/128K OSC/8K OSC/4K OSC/2K WATCHDOG RESET OSC/32K WATCHDOG PRESCALER 128 kHz OSCILLATOR OSC/16K Figure 9-7. WDP0 WDP1 WDP2 WDP3 WDE MCU RESET 9.
9.4 9.4.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description MCUSR • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.
ATtiny261/461/861 the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 9-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
Table 9-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32764) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATtiny261/461/861 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
10. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny261/461/861. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 13. 10.1 Interrupt Vectors in ATtiny261/461/861 Table 10-1. Reset and Interrupt Vectors Vector No.
ATtiny261/461/861 0x0007 rjmp USI_START ; USI Start Handler 0x0008 rjmp USI_OVF ; USI Overflow Handler 0x0009 rjmp EE_RDY ; EEPROM Ready Handler 0x000A rjmp ANA_COMP ; Analog Comparator Handler 0x000B rjmp ADC ; ADC Conversion Handler 0x000C rjmp WDT ; WDT Interrupt Handler 0x000D rjmp EXT_INT1 ; IRQ1 Handler 0x000E rjmp TIM0_COMPA ; Timer0 CompareA Handler 0x000F rjmp TIM0_COMPB ; Timer0 CompareB Handler 0x0010 rjmp TIM0_CAPT ; Timer0 Capture Event Handler 0x0011 rj
11. External Interrupts The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT15..0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..
ATtiny261/461/861 11.1.2 GIMSK – General Interrupt Mask Register Bit 7 6 5 4 3 2 1 0x3B (0x5B) INT1 INT0 PCIE1 PCIE0 – – – 0 – Read/Write R/W R/W R/W R/w R R R R Initial Value 0 0 0 0 0 0 0 0 GIMSK • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
ATtiny261/461/861 12. I/O Ports 12.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2.
ATtiny261/461/861 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.
Figure 12-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATtiny261/461/861 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
12.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATtiny261/461/861 Figure 12-5.
Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 12-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATtiny261/461/861 12.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 12-3. Table 12-3.
ADC8: ADC input Channel 8. Note that ADC input channel 8 uses analog power. PCINT13: Pin Change Interrupt source 13. • Port B, Bit 4 - XTAL1/ CLKI/ OC1B/ ADC7/ PCINT12 XTAL1/CLKI: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
ATtiny261/461/861 • Port B, Bit 0 - MOSI/ DI/ SDA/ OC1A/ PCINT8 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit. DI: Data Input in USI Three-wire mode.
Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals shown in Figure 12-5 on page 59. Table 12-4. Overriding Signals for Alternate Functions in PB7..
ATtiny261/461/861 12.3.2 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 12-6. Table 12-6.
PCINT3: Pin Change Interrupt source 3. • Port A, Bit 2 - ADC2/INT1/USCK/SCL/PCINT2 ADC2: Analog to Digital Converter, Channel 2. INT1: The PA2 pin can serve as an External Interrupt source 1. USCK: Three-wire mode Universal Serial Interface Clock. SCL: Two-wire mode Serial Clock for USI Two-wire mode. PCINT2: Pin Change Interrupt source 2. • Port A, Bit 1 - ADC1/DO/PCINT1 ADC1: Analog to Digital Converter, Channel 1. DO: Three-wire mode Universal Serial Interface Data output.
ATtiny261/461/861 Table 12-8. Overriding Signals for Alternate Functions in PA3..
12.4 12.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) - PUD SE SM1 SM0 - ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATtiny261/461/861 13. Timer/Counter0 Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. See Table 13-1 on page 71 for details. 13.0.
An external clock source can not be prescaled. Figure 13-2. Prescaler for Timer/Counter0 clk I/O Clear PSR0 T0 Synchronization clkT0 Note: 13.1 13.1.1 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.
ATtiny261/461/861 Table 13-1. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
14. Timer/Counter0 14.1 Features • • • • • 14.2 Clear Timer on Compare Match (Auto Reload) Input Capture unit Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0) 8-bit Mode with Two Independent Output Compare Units 16-bit Mode with One Independent Output Compare Unit Overview Timer/Counter0 is a general purpose 8-/16-bit Timer/Counter module, with two/one Output Compare units and Input Capture feature. The Timer/Counter0 general operation is described in 8-/16-bit mode.
ATtiny261/461/861 14.2.2 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing Timer/Counter0 counter value and so on.
internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the counter reaches the maximum value and it can be used for generating a CPU interrupt. 14.
ATtiny261/461/861 Figure 14-2. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
14.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP0 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
ATtiny261/461/861 14.6.1 Input Capture Trigger Source The default trigger source for the Input Capture unit is the Input Capture pin (ICP0). Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture Enable (ACIC0) bit in the Timer/Counter Control Register A (TCCR0A). Be aware that changing trigger source can trigger a capture.
when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Figure 14-4 shows a block diagram of the Output Compare unit. Figure 14-4. Output Compare Unit, Block Diagram DATA BUS TCNTn OCRnx = (8/16-bit Comparator ) OCFnx (Int.Req.) 14.7.1 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped.
ATtiny261/461/861 Figure 14-6. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-7 shows the setting of OCF0A and OCF0B in Normal mode. Figure 14-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 14-8.
14.9 Accessing Registers in 16-bit Mode In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers.
ATtiny261/461/861 The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example ... ; Set TCNT0 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT0H,r17 out TCNT0L,r16 ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ... C Code Example unsigned int i; ...
The following code examples show how to do an atomic read of the TCNT0 register contents. Reading any of the OCR0 register can be done by using the same principle.
ATtiny261/461/861 The following code examples show how to do an atomic write of the TCNT0H/L register contents. Writing any of the OCR0A/B registers can be done by using the same principle.
14.10 Register Description 14.10.1 TCCR0A – Timer/Counter0 Control Register A Bit 7 6 5 4 3 2 1 0 0x15 (0x35) TCW0 ICEN0 ICNC0 ICES0 ACIC0 – – WGM00 Read/Write R/W R/W R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7– TCW0: Timer/Counter0 Width When this bit is written to one 16-bit mode is selected as described Figure 14-5 on page 78.
ATtiny261/461/861 Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ”Modes of Operation” on page 74). 14.10.2 TCNT0L – Timer/Counter0 Register Low Byte Bit 7 6 5 0x32 (0x52) 4 3 2 1 0 TCNT0L[7:0] TCNT0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter0 Register Low Byte, TCNT0L, gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Register. To ensure that both the high and the low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing Registers in 16-bit Mode” on page 80. 14.10.
ATtiny261/461/861 14.10.7 TIFR – Timer/Counter0 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 4– OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0.
15. Timer/Counter1 Prescaler Figure 15-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (‘1’). Figure 15-1.
ATtiny261/461/861 15.1 15.1.1 Register Description PLLCSR – PLL Control and Status Register Bit 7 6 5 4 3 2 1 0 0x29 (0x49) LSM - - - - PCKE PLLE PLOCK Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 PLLCSR • Bit 7- LSM: Low Speed Mode The Low Speed mode is selected, if the LSM bit is written to one, and then the fast peripheral clock is scaled down from 64 MHz to 32 MHz.
When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. • Bits 3:0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 15-1.
ATtiny261/461/861 16. Timer/Counter1 16.1 Features • • • • • • • • • 16.
Figure 16-1.
ATtiny261/461/861 Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 High Byte Register (TC1H) is a 2-bit register that is used as a common temporary buffer to access the MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used. Interrupt request (overflow TOV1, and compare matches OCF1A, OCF1B, OCF1D and fault protection FPF1) signals are visible in the Timer Interrupt Flag Register (TIFR) and Timer/Counter1 Control Register D (TCCR1D).
Figure 16-2. Timer/Counter1 Synchronization Register Block Diagram.
ATtiny261/461/861 16.3 Counter Unit The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 163 shows a block diagram of the counter and its surroundings. Figure 16-3. Counter Unit Block Diagram DATA BUS TOV1 clkT1 Timer/Counter1 Count Enable ( From Prescaler ) count TCNT1 clear Control Logic direction PCKE PCK CK bottom top Signal description (internal signals): count TCNT1 increment or decrement enable. direction Select between increment and decrement.
16.4 Output Compare Unit The comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A, OCR1B, OCR1C and OCR1D). Whenever TCNT1 equals to the Output Compare Register, the comparator signals a match. A match will set the Output Compare Flag (OCF1A, OCF1B or OCF1D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
ATtiny261/461/861 Figure 16-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value Output Compare Waveform OCWnx Synchronized WFnx Latch Compare Value changes Counter Value Compare Value Unsynchronized WFnx Latch Glitch Output Compare Wafeform OCWnx 16.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit.
16.5 Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs OC1x and OC1x when the PWM mode is enabled and the COM1x1:0 bits are set to “01”.
ATtiny261/461/861 The length of the counting period is user adjustable by selecting the dead time prescaler setting by using the DTPS11:10 control bits, and selecting then the dead time value in I/O register DT1. The DT1 register consists of two 4-bit fields, DT1H and DT1L that control the dead time periods of the PWM output and its' complementary output separately in terms of the number of prescaled dead time generator clock cycles.
Figure 16-9.
ATtiny261/461/861 16.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (bits PWM1x and WGM10) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted, non-inverted or complementary.
toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM1x1:0 = 1). The OC1x value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC1x = fclkT1/4 when OCR1C is set to zero.
ATtiny261/461/861 Figure 16-11. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCWnx (COMnx1:0 = 2) OCWnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins.
Table 16-3. 16.7.3 Output Compare Pin Configurations in Fast PWM Mode COM1x1 COM1x0 OC1x Pin OC1x Pin 0 0 Disconnected Disconnected 0 1 OC1x OC1x 1 0 Disconnected OC1x 1 1 Disconnected OC1x Phase and Frequency Correct PWM Mode The Phase and Frequency Correct PWM Mode (PWMx = 1 and WGM10 = 1) provides a high resolution Phase and Frequency Correct PWM waveform generation option. The Phase and Frequency Correct PWM mode is based on a dual-slope operation.
ATtiny261/461/861 In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and setting the COM1x1:0 to three will produce an inverted PWM output. Setting the COM1A1:0 bits to one will enable complementary Compare Output mode and produce both the non-inverted (OC1x) and inverted output (OC1x).
Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches the TOP and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. Whereas, if the dual-slope operation is selected (the WGM10 bit is set to 1), the counter counts repeatedly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM like in Phase and Frequency Correct PWM Mode.
ATtiny261/461/861 and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the port pin. The Output Compare Pin configurations are described in Table 16-5. Table 16-5. 16.
Figure 16-15. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 TOVn Figure 16-16. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) OCRnx - 1 TCNTn OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 16-17. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8) clkPCK clkTn (clkPCK /8) TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1 TOVn 16.
ATtiny261/461/861 When the Fault Protection mode is enabled by the Fault Protection Enable (FPEN1) bit and a change of the logic level (an event) occurs on the external interrupt pin (INT0), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a Fault Protection mode will be triggered.
16.10 Accessing 10-Bit Registers If 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 10-bit registers can be byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The 10-bit registers have a common 2-bit Timer/Counter1 High Byte Register (TC1H) that is used for temporary storing of the two MSBs of the 10-bit access. The same TC1H register is shared between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation.
ATtiny261/461/861 It is important to notice that accessing 10-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 10-bit register, and the interrupt code updates the TC1H register by accessing the same or any other of the 10-bit timer registers, then the result of the access outside the interrupt will be corrupted.
The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle.
ATtiny261/461/861 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1A • Bits 7,6 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1A) and the connection of the Output Compare pin (OC1A).
Table 16-8 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits are set to Phase and Frequency Correct PWM Mode. Table 16-8. COM1A1..0 Compare Output Mode, Phase and Frequency Correct PWM Mode OCW1A Behaviour OC1A Pin OC1A Pin Disconnected Disconnected 00 Normal port operation. 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting.
ATtiny261/461/861 that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the output driver. The function of the COM1B1:0 bits depends on the PWM1B and WGM10 bit settings. Table 1611 shows the COM1B1:0 bit functionality when the PWM1B bit is set to Normal Mode (nonPWM). Table 16-11. Compare Output Mode, Normal Mode (non-PWM) COM1B1..0 OCW1B Behaviour OC1B Pin OC1B Pin Disconnected Disconnected 00 Normal port operation. 01 Toggle on Compare Match.
value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit is always read as zero. • Bit 2 - FOC1B: Force Output Compare Match 1B The FOC1B bit is only active when the PWM1B bit specify a non-PWM mode. Writing a logical one to this bit forces a change in the Waveform Output (OCW1B) and the Output Compare pin (OC1B) according to the values already set in COM1B1 and COM1B0.
ATtiny261/461/861 Table 16-14. Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T/C1 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8x • Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 16-15.
• Bits 5,4 - COM1B1S, COM1B0S: Comparator B Output Mode, Bits 1 and 0 These bits are the shadow bits of the COM1A1 and COM1A0 bits that are described in the section ”TCCR1A – Timer/Counter1 Control Register A” on page 113. • Bits 3,2 - COM1D1, COM1D0: Comparator D Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1D) and the connection of the Output Compare pin (OC1D).
ATtiny261/461/861 Table 16-18. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1D1..0 OCW1D Behaviour OC1D Pin OC1D Pin Disconnected Disconnected 00 Normal port operation. 01 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Connected 10 Cleared on Compare Match when up-counting. Set on Compare Match when down-counting. Connected Disconnected 11 Set on Compare Match when up-counting. Cleared on Compare Match when down-counting.
• Bit 3 - FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Fault Protection interrupt.
ATtiny261/461/861 the Output Compare Override Enable Bit is cleared. Table 16-20 shows the Output Compare Override Enable Bits and their corresponding Output Compare pins. Table 16-20. Output Compare Override Enable Bits vs. Output Compare Pins 16.11.
The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event.
ATtiny261/461/861 16.11.11 OCR1D – Timer/Counter1 Output Compare Register D Bit 7 6 5 4 3 2 1 0 0x2A (0x4A) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1D The output compare register D is an 8-bit read/write register. The Timer/Counter Output Compare Register D contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1A.
16.11.13 TIFR – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TIFR • Bit 7- OCF1D: Output Compare Flag 1D The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing the corresponding interrupt handling vector.
ATtiny261/461/861 • Bits 7:4- DT1H3:DT1H0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. • Bits 3:0- DT1L3:DT1L0: Dead Time Value for OC1x Output The dead time value for the OC1x output. The dead time delay is set as a number of the prescaled timer/counter clocks.
17. USI – Universal Serial Interface 17.1 Features • • • • • • 17.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication.
ATtiny261/461/861 The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
Figure 17-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 17-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATtiny261/461/861 rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
17.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATtiny261/461/861 Figure 17-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 17-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used.
1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the USI Data Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 17-6.) detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2.
ATtiny261/461/861 17.4 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 17.4.1 Half-duplex Asynchronous Data Transfer By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 17.4.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
17.5.2 USIBR – USI Buffer Register Bit 7 0x10 (0x30) MSB 6 5 4 3 2 1 Read/Write Initial Value 0 R R R R R R R R 0 0 0 0 0 0 0 0 LSB USIBR The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data.
ATtiny261/461/861 The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1).
Table 17-1. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATtiny261/461/861 Table 17-2. Relations between the USICS1..
18. AC – Analog Comparator The Analog Comparator compares the input values on the selectable positive pin (AIN0, AIN1 or AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is higher than the voltage on the negative pin, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
ATtiny261/461/861 • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
18-2. If ACME is cleared or ADEN is set, either AIN0, AIN1 or AIN2 is applied to the negative input to the Analog Comparator. Table 18-2. 140 Analog Comparator Multiplexed Input ACME ADEN MUX5..0 ACM2..
ATtiny261/461/861 Table 18-2. 18.2.1 Analog Comparator Multiplexed Input (Continued) ACME ADEN MUX5..0 ACM2..
19. ADC – Analog to Digital Converter 19.1 Features • • • • • • • • • • • • • • • • • • 19.2 10-bit Resolution 1.0 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels 16 Differential input pairs 15 Differential input pairs with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
ATtiny261/461/861 Figure 19-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADATE ADIF ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER A (ADCSRA) ADLAR MUX1 MUX0 MUX3 MUX2 MUX4 REFS1 REFS0 ADC MULTIPLEXER SELECT (ADMUX) MUX5 REFS2 GSEL ADC CTRL. & STATUS REGISTER B (ADCSRB) ADIE ADIF 8-BIT DATA BUS PRESCALER MUX DECODER AREF INTERNAL 2.56/1.
If the same ADC input pin is selected as both the positive and negative input to the differential gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW. The on-chip temperature sensor is selected by writing the code “111111” to the MUX5..
ATtiny261/461/861 Figure 19-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
ATtiny261/461/861 Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 19-7.
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
ATtiny261/461/861 interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 19.7.
19.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 19.7.3 b.
ATtiny261/461/861 Figure 19-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 19-11.
Figure 19-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATtiny261/461/861 155). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x, 8x, 20x or 32x. 19.8.3 Bipolar Differential Conversion As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writting the BIN bit in the ADCSRB to one.
where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sensor offset value determined and stored into EEPROM. 19.10 Register Descriptin 19.10.
ATtiny261/461/861 Table 19-4. Input Channel Selections MUX5..
Table 19-4.
ATtiny261/461/861 19.10.2 ADCSRA – ADC Control and Status Register A Bit 7 0x06 (0x26) 6 ADEN 5 ADSC 4 ADATE 3 ADIF 2 ADIE ADPS2 1 0 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
Table 19-5. 19.10.3 19.10.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial Value 19.10.3.
ATtiny261/461/861 • Bits 7– BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference.
19.10.5 DIDR0 – Digital Input Disable Register 0 Bit 7 6 5 4 3 2 1 0 0x01 (0x21) ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 • Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set.
ATtiny261/461/861 20. debugWIRE On-chip Debug System 20.1 Features • • • • • • • • • • 20.
When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 20.
ATtiny261/461/861 21. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 21.1 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
ATtiny261/461/861 21.1.2 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
21.1.4 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 21-1 shows the typical programming time for Flash accesses from the CPU. Table 21-1. Symbol Min Programming Time Max Programming Time Flash write (Page Erase, Page Write, and write Lock bits by SPM) 3.7 ms 4.5 ms Note: 21.2 21.2.1 SPM Programming Time(1) 1. Minimum and maximum programming time is per individual operation.
ATtiny261/461/861 • Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
22. Memory Programming This section describes the different methods for Programming the ATtiny261/461/861 memories. 22.1 Program And Data Memory Lock Bits The ATtiny261/461/861 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 22-2. The Lock bits can only be erased to “1” with the Chip Erase command. The ATtiny261/461/861 has no separate Boot Loader section.
ATtiny261/461/861 22.2 Fuse Bytes The ATtiny261/461/861 has three Fuse bytes. Table 22-3, Table 22-4 and Table 22-5 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 22-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Table 22-4.
Table 22-5. Fuse Low Byte Fuse Low Byte Description Default Value 7 Divide clock by 8 0 (programmed) CKOUT(2) 6 Clock Output Enable 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(3) SUT0 4 Select start-up time 0 (programmed)(3) CKSEL3 3 Select Clock source 0 (programmed)(4) CKSEL2 2 Select Clock source 0 (programmed)(4) CKSEL1 1 Select Clock source 1 (unprogrammed)(4) CKSEL0 0 Select Clock source 0 (programmed)(4) (1) CKDIV8 Notes: Bit No 1.
ATtiny261/461/861 22.5 Page Size Table 22-7. Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATtiny261 1K words (2K bytes) 16 words PC[3:0] 64 PC[9:4] 9 ATtiny461 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 ATtiny861 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Table 22-8. 22.6 No. of Words in a Page and No. of Pages in the Flash No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No.
Figure 22-1. Parallel Programming +5V WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 VCC +5V AVCC PA7 - PA0 DATA XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Table 22-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O WR PB0 I Write Pulse (Active low). XA0 PB1 I XTAL Action Bit 0 XA1/BS2 PB2 I XTAL Action Bit 1. Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). PAGEL/BS1 PB3 I Byte Select 1 (“0” selects low byte, “1” selects high byte).
ATtiny261/461/861 Table 22-11. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 22-12. Command Byte Bit Coding Command Byte 22.7 22.7.
22.7.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”.
ATtiny261/461/861 While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 22-2 on page 175. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”.
Figure 22-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D DATA HIGH E XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Note: 22.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 22-8 on page 171. When programming the EEPROM, the program data is latched into a page buffer.
ATtiny261/461/861 Figure 22-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C E DATA XX B ADDR. LOW C DATA E L XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 22.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on page 174 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4.
22.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 174 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 22.7.
ATtiny261/461/861 22.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 174 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
22.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 174 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”. 22.7.
ATtiny261/461/861 22.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 22-13 on page 181, the pin mapping for SPI programming is listed.
22.8.1 Serial Programming Algorithm When writing serial data to the ATtiny261/461/861, data is clocked on the rising edge of SCK. When reading data from the ATtiny261/461/861, data is clocked on the falling edge of SCK. See Figure 23-7 and Figure 23-8 for timing details. To program and verify the ATtiny261/461/861 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 22-15): 1.
ATtiny261/461/861 Table 22-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 22.8.2 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Serial Programming Instruction set Table 22-15 on page 183 and Figure 22-8 on page 184 describes the Instruction set. Table 22-15.
Table 22-15. Serial Programming Instruction Set (Continued) Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Notes: 1. 2. 3. 4. 5. 6. 7. Not all instructions are applicable for all parts. a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
ATtiny261/461/861 23. Electrical Characteristics 23.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Condition Typ. Max. Units (6) Min. 0.4 0.6 mA (6) 2 3 mA (6) Active 8MHz, VCC = 5V 6 9 mA Idle 1MHz, VCC = 2V(6) 0.1 0.3 mA Idle 4MHz, VCC = 3V(6) 0.4 1 mA 1.5 3 mA 4 10 µA 0.
ATtiny261/461/861 23.3 Speed Grades Figure 23-1. Maximum Frequency vs. VCC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 23-2. Maximum Frequency vs. VCC 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.
23.4 Clock Characteristics 23.4.1 Calibrated Internal RC Oscillator Accuracy Table 23-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±10% User Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40°C - 85°C ±1% Notes: 1. Voltage range for ATtiny261V/461V/861V. 2. Voltage range for ATtiny261/461/861. 23.4.2 External Clock Drive Waveforms Figure 23-3.
ATtiny261/461/861 23.5 System and Reset Characteristics Table 23-3. Symbol VPOT Reset, Brown-out and Internal Voltage Characteristics(1) Parameter Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) TA = -40 - 85°C 0.7 1.0 1.4 V Power-on Reset Threshold Voltage (falling)(2) TA = -40 - 85°C 0.6 0.9 1.3 V 0.2 VCC 0.9 VCC V 2.
23.6 ADC Characteristics – Preliminary Data Table 23-5. Symbol ADC Characteristics, Single Ended Channels. -40°C - 85°C Parameter Resolution Condition Single Ended Conversion Units 10 Bits LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny261/461/861 23.7 Parallel Programming Characteristics Figure 23-4. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX tBVPH tPLBX t BVWL Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) tWLBX tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 23-5.
Figure 23-6. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV PAGEL/BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 192 1. The timing requirements shown in Figure 23-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
ATtiny261/461/861 Table 23-6. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
23.8 Serial Programming Characteristics Figure 23-7. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Figure 23-8. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 23-7. Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny261/461/861V) tCLCL Oscillator Period (ATtiny261/461/861V) Min Typ 0 Max Units 4 MHz 250 1/tCLCL Oscillator Frequency (ATtiny261/461/861L, VCC = 2.7 - 5.
ATtiny261/461/861 24. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
Figure 24-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 16 ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 24-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
ATtiny261/461/861 Figure 24-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1,6 85 ˚C 25 ˚C 1,4 I CC (mA) 1,2 -40 ˚C 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs.
24.2 Idle Supply Current Figure 24-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,3 5.5 V 0,25 I CC (mA) 5.0 V 0,2 4.5 V 4.0 V 0,15 3.3 V 2.7 V 0,1 1.8 V 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 24-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz ICC (mA) 4,5 4 5.5 V 3,5 5.0 V 3 4.5 V 2,5 4.0 V 2 1,5 3.3 V 1 2.7 V 0,5 1.
ATtiny261/461/861 Figure 24-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 2,5 85 ˚C 25 ˚C -40 ˚C ICC (mA) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs.
Figure 24-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,2 85 ˚C 0,18 0,16 I CC (mA) 0,14 0,12 0,1 25 ˚C 0,08 -40 ˚C 0,06 0,04 0,02 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 24.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
ATtiny261/461/861 Example Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI enabled at VCC = 2.0V and F = 1MHz. From Table 24-2, third column, we see that we need to add 10% for the TIMER0, 27.3 % for the ADC, and 6.5 % for the USI module. Reading from Figure 24-6 on page 198, we find that the idle current consumption is ~0,085 mA at VCC = 2.0V and F=1MHz.
24.5 Pin Pull-up Figure 24-13. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 60 50 IOP (uA) 40 30 20 25 ˚C 10 85 ˚C -40 ˚C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 24-14. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.
ATtiny261/461/861 Figure 24-15. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 140 120 IOP (uA) 100 80 60 40 25 ˚C 85 ˚C -40 ˚C 20 0 0 1 2 3 4 5 6 VOP (V) Figure 24-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.
Figure 24-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 70 60 IRESET(uA) 50 40 30 20 25 ˚C 10 -40 ˚C 85 ˚C 0 0 0,5 1 1,5 2 2,5 3 VRESET(V) Figure 24-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
ATtiny261/461/861 24.6 Pin Driver Strength Figure 24-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0,9 85 ˚C 0,8 0,7 25 ˚C VOL (V) 0,6 -40 ˚C 0,5 0,4 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 24-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs.
Figure 24-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3,1 2,9 2,7 VOH (V) 2,5 -40 ˚C 2,3 25 ˚C 2,1 85 ˚C 1,9 1,7 1,5 0 5 10 15 20 25 IOH (mA) Figure 24-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs.
ATtiny261/461/861 24.7 Pin Threshold and Hysteresis Figure 24-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3,5 -40 ˚C Threshold (V) 3 25 ˚C 85 ˚C 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-24. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 24-25. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0,7 Input Hysteresis (mV) 0,6 -40 ˚C 25 ˚C 85 ˚C 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-26. Reset Input Threshold Voltage vs. VCC (VIH, Reset Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs.
ATtiny261/461/861 Figure 24-27. Reset Input Threshold Voltage vs. VCC (VIL, Reset Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2,5 85 ˚C 25 ˚C -40 ˚C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-28. Reset Pin input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs.
24.8 BOD Threshold and Analog Comparator Offset Figure 24-29. BOD Threshold vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 4.3V 4,5 4,45 Threshold (V) 4,4 4,35 Rising VCC 4,3 4,25 Falling VCC 4,2 4,15 4,1 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 24-30. BOD Threshold vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 2.
ATtiny261/461/861 Figure 24-31. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL is 1.8V 2 1,95 Threshold (V) 1,9 1,85 Rising VCC 1,8 Falling VCC 1,75 1,7 1,65 1,6 -60 -40 -20 0 20 40 60 80 100 Temperature (C) 24.9 Internal Oscillator Speed Figure 24-32. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs.
Figure 24-33. Calibrated 8.0 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. VCC 9 8,8 8,6 85 ˚C FRC (MHz) 8,4 8,2 25 ˚C 8 7,8 -40 ˚C 7,6 7,4 7,2 7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-34. Calibrated 8.0 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 9 8,8 8,6 5.0 V FRC (MHz) 8,4 8,2 3.
ATtiny261/461/861 Figure 24-35. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 85 ˚C 16 25 ˚C 14 -40 ˚C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 24.10 Current Consumption of Peripheral Units Figure 24-36. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs.
Figure 24-37. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 180 25 ˚C 150 ICC (uA) 120 90 60 30 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-38. Analog Comparator vs. VCC ANALOG COMPARATOR vs.
ATtiny261/461/861 Figure 24-39. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 85 ˚C 25 ˚C 25 -40 ˚C I CC (uA) 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 24-40. Programming Current vs. VCC PROGRAMMING CURRENT vs.
Figure 24-41. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 10 -40 ˚C 85 ˚C 25 ˚C 9 8 ICC (uA) 7 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 24.11 Current Consumption in Reset and Reset Pulsewidth Figure 24-42. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. Low Frequency 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0,14 5.5 V 0,12 5.0 V ICC (mA) 0,1 4.5 V 0,08 4.
ATtiny261/461/861 Figure 24-43. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 2,5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1,5 4.0 V 1 3.3 V 0,5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 24-44. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
25.
ATtiny261/461/861 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
26.
ATtiny261/461/861 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
27. Ordering Information 27.1 ATtiny261 Speed (MHz)(3) 10 20 Notes: Power Supply Ordering Code(2) Package(1) 1.8 - 5.5V ATtiny261V-10MU ATtiny261V-10PU ATtiny261V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny261-20MU ATtiny261-20PU ATtiny261-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATtiny261/461/861 27.2 ATtiny461 Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) 10 1.8 - 5.5V ATtiny461V-10MU ATtiny461V-10PU ATtiny461V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny461-20MU ATtiny461-20PU ATtiny461-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
27.3 ATtiny861 Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) 10 1.8 - 5.5V ATtiny861V-10MU ATtiny861V-10PU ATtiny861V-10SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) 20 2.7 - 5.5V ATtiny861-20MU ATtiny861-20PU ATtiny861-20SU 32M1-A 20P3 20S2 Industrial (-40°C to 85°C) Notes: Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATtiny261/461/861 28. Packaging Information 28.1 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b K 0.20 REF 0.18 e L BOTTOM VIEW D1 4.75 BSC 2.95 E1 E2 3.10 3.25 5.00 BSC 4.75BSC 2.95 e Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 0.30 5.00 BSC E b 0.
28.2 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.493 – 25.984 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.
ATtiny261/461/861 28.
29. Errata 29.1 Errata ATtiny261 The revision letter in this section refers to the revision of the ATtiny261 device. 29.1.1 Rev A No known errata. 29.2 Errata ATtiny461 The revision letter in this section refers to the revision of the ATtiny461 device. 29.2.1 Rev B Yield improvement. No known errata. 29.2.2 Rev A No known errata. 29.3 Errata ATtiny861 The revision letter in this section refers to the revision of the ATtiny861 device. 29.3.1 Rev B No known errata. 29.3.2 Rev A Not sampled.
ATtiny261/461/861 30. Datasheet Revision History 30.1 Rev. 2588A – 11/06 1. 2. 30.2 Updated ”Ordering Information” on page 222. Updated ”Packaging Information” on page 225. Rev. 2588A – 10/06 1. Initial Revision.
ATtiny261/461/861 2588B–AVR–11/06
ATtiny261/461/861 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Disclaimer .................................................................................................................2 2 Overview ................................................................................................... 3 2.
7.10 Clock Output Buffer ..............................................................................................31 7.11 System Clock Prescaler .......................................................................................31 7.12 Register Description .............................................................................................32 8 Power Management and Sleep Modes ................................................. 34 8.1 Sleep Modes ............................................
ATtiny261/461/861 14.6 Input Capture Unit ................................................................................................76 14.7 Output Compare Unit ............................................................................................77 14.8 Timer/Counter Timing Diagrams ..........................................................................78 14.9 Accessing Registers in 16-bit Mode .....................................................................80 14.
19.6 Changing Channel or Reference Selection ........................................................147 19.7 ADC Noise Canceler ..........................................................................................148 19.8 ADC Conversion Result ......................................................................................152 19.9 Temperature Measurement ................................................................................153 19.10 Register Descriptin .................................
ATtiny261/461/861 24.1 Active Supply Current .........................................................................................195 24.2 Idle Supply Current .............................................................................................198 24.3 Supply Current of I/O modules ...........................................................................200 24.4 Power-down Supply Current ...............................................................................201 24.5 Pin Pull-up .......
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