Manual

46
ATtiny26(L)
1477B–AVR–04/02
Figure 33. Timer/Counter0 Block Diagram
Timer/Counter0 Control
Register – TCCR0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and always read as zero.
• Bit 3 – PSR0: Prescaler Reset Timer/Counter0
When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will
be cleared by hardware after the operation is performed. Writing a zero to this bit will
have no effect. This bit will always be read as zero.
Bit 7 6 5 4 3 210
$33 ($53) –– – –PSR0 CS02 CS01 CS00 TCCR0
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0