Features • High-performance, Low-power AVR ® 8-bit Microcontroller • RISC Architecture • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz Data and Non-volatile Program Memory – 2K Bytes of In-System Programmable Program Memory Flash Endurance: 1,000 Write/Erase Cycles – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM
Pin Configuration PDIP/SOIC/SSOP (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (AREF) GND AVCC PA4 (ADC3) PA5 (ADC4) PA6 (ADC5/AIN0) PA7 (ADC6/AIN1) 32 31 30 29 28 27 26 25 PB2 (SCK/SCL/OC1B) PB1 (MISO/DO/OC1A) PB0 (MOSI/DI/SDA/OC1A) NC NC NC PA0 (ADC0) PA1 (ADC1) MLF Top View 24 23 22 21 20 19 18 17 1 2 3 4 5
ATtiny26(L) Description The ATtiny26/L is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny26/L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers.
Block Diagram Figure 1.
ATtiny26(L) Pin Descriptions VCC Digital supply voltage pin. GND Digital ground pin. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 77 for details on operating of the ADC. Port A (PA7..PA0) Port A is an 8-bit general purpose I/O port. PA7..
Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as 16-bit pointers for indirect memory access.
ATtiny26(L) pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System programmable Flash memory. With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
All of the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31.
ATtiny26(L) In-System Programmable Flash Program Memory The ATtiny26/L contains 2K bytes On-chip In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATtiny26/L Program Counter – PC – is 10 bits wide, thus addressing the 1024 program memory addresses, see “Memory Programming” on page 106 for a detailed description on Flash data downloading.
Program and Data Addressing Modes The ATtiny26/L AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Flash program memory, SRAM, Register File, and I/O Data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Register Direct, Single Register Rd Figure 6.
ATtiny26(L) I/O Direct Figure 8. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 9. Direct Data Addressing Data Space 20 19 31 OP $0000 16 Rr/Rd 16 LSBs 15 0 $00DF A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 10.
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 11. Data Indirect Addressing Data Space $0000 15 0 X-, Y-, OR Z-REGISTER $00DF Operand address is the contents of the X-, Y-, or the Z-register. Data Indirect with Predecrement Figure 12. Data Indirect Addressing with Pre-decrement Data Space $0000 15 0 X-, Y-, OR Z-REGISTER -1 $00DF The X-, Y-, or Z-register is decremented before the operation.
ATtiny26(L) The X-, Y-, or Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or Z-register prior to incrementing. Constant Addressing Using the LPM Instruction Figure 14. Code Memory Constant Addressing PROGRAM MEMORY $000 $3FF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 15.
Relative Program Addressing, RJMP and RCALL Figure 16. Relative Program Memory Addressing PROGRAM MEMORY $000 +1 $3FF Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047. EEPROM Data Memory The ATtiny26/L contains 128 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location.
ATtiny26(L) Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 17 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
Figure 19. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø WR Data RD 16 Address Write Data Prev.
ATtiny26(L) I/O Memory The I/O space definition of the ATtiny26/L is shown in Table 1 Table 1.
Table 1. ATtiny26/L I/O Space(1) (Continued) Address Hex Name $06($26) ADCSR $05($25) ADCH ADC Data Register High $04($24) ADCL ADC Data Register Low Note: Function ADC Control and Status Register 1. Reserved and unused locations are not shown in the table. All ATtiny26/L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space.
ATtiny26(L) • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation.
Reset and Interrupt Handling The ATtiny26/L provides eleven interrupt sources. These interrupts and the separate Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors.
ATtiny26(L) Reset Sources The ATtiny26/L provides four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). • External Reset. To use the PB7/RESET pin as an External Reset, instead of I/O pin, unprogram (“1”) the RSTDISBL Fuse. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. • Brown-out Reset.
0 Table 3. Reset Characteristics Symbol VPOT Parameter Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.4 2.3 V Power-on Reset Threshold Voltage (falling)(1) 1.3 2.3 V 0.9 VCC VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin Brown-out Reset Threshold Voltage(2) BODLEVEL = 1 2.5 2.7 3.2 VBOT BODLEVEL = 0 3.7 4.0 4.
ATtiny26(L) Figure 21. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 22. MCU Start-up, RESET Controlled Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Brown-out Detection ATtiny26/L has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and VCC decreases below the trigger level, the Brown-out Reset is immediately activated. When VCC increases above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 2.
ATtiny26(L) System Clock and Clock Options Clock Systems and their Distribution Figure 26 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 26.
Internal PLL for Fast Peripheral Clock Generation – clkPCK The internal PLL in ATtiny26/L generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is automatically divided down to 1 MHz, if needed. See the Figure 27 on page 26. When the PLL reference frequency is the nominal 1 MHz, the fast peripheral clock is 64 MHz.
ATtiny26(L) Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below on Table 4. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.The use of pins PB5 (XTAL2), and PB4 (XTAL1) as I/O pins is limited depending on clock settings, as shown below in Table 5. Table 4. Device Clocking Options Select Device Clocking Option PLLCK CKSEL3..
each time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. The device is shipped with PLLCK = “1”, CKSEL = “0001”, and SUT = “10” (1 MHz Internal RC Oscillator, slowly rising power). Table 6. Number of Watchdog Oscillator Cycles Crystal Oscillator Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 4.1 ms 4.
ATtiny26(L) The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 8. Table 8. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down Additional Delay from Reset (VCC = 5.0V) 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 29 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 29.
ATtiny26(L) Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 12. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 14. Table 14. Internal RC Oscillator Frequency Range. External Clock OSCCAL Value Min Frequency in Percentage of Nominal Frequency Max Frequency in Percentage of Nominal Frequency $00 50% 100% $7F 75% 150% $FF 100% 200% To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 30.
ATtiny26(L) High Frequency PLL Clock – PLLCLK There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as a system clock source, by programming (“0”) the fuse PLLCK, it is divided by four. When this option is used, the CKSEL3..0 must be set to “0001”. This clocking option can be used only when operating between 4.5 - 5.5V.
Interrupt Handling The ATtiny26/L has two 8-bit Interrupt Mask Control Registers; GIMSK – General Interrupt Mask Register and TIMSK – Timer/Counter Interrupt Mask Register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction – RETI – is executed.
ATtiny26(L) The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupt” on page 38. • Bit 5 – PCIE1: Pin Change Interrupt Enable1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the interrupt pin change is enabled on analog pins PB[7:4], PA[7:6] and PA[3]. Unless the alternate function masks out the interrupt, any change on the pin mentioned before will cause an interrupt.
Timer/Counter Interrupt Mask Register – TIMSK Bit 7 6 5 4 3 2 1 $39 ($59) – OCIE1A OCIE1B – – TOIE1 TOIE0 0 – Read/Write R R/W R/W R R R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26/L and always reads as zero.
ATtiny26(L) Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 $38 ($58) – OCF1A OCF1B – – TOV1 TOV0 – Read/Write R R/W R/W R R R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26/L and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A – Output Compare Register 1A.
External Interrupt The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is configured as an output. This feature provides a way of generating a software interrupt. The External Interrupt can be triggered by a falling or rising edge, a pin change, or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR.
ATtiny26(L) Table 17. Alternative Functions (Continued) Bit or Fuse Value(2) Alternate Function PB4 XTAL1, clock source FUSE[PLLCK,CKSEL] FUSE[PLLCK,CKSEL] 10000 10101-11111 PB5 XTAL2, clock source FUSE[PLLCK,CKSEL] 11001-11111 PB6 External interrupt TC0 clock GIMSK[INT0],MCUCR[ISC01,ISC01] TCCR0[CS02,CS01] 100 11 PB7 RESET RSTDISBL FUSE 1 Notes: MCU Control Register – MCUCR Control Register[Bit Name] which set the Alternate Function(1) Pin 1.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set (one). The activity on the external INT0 pin that activates the interrupt is defined in the following table. Table 19. Interrupt 0 Sense Control(1) ISC01 ISC00 0 0 The low level of INT0 generates an interrupt request. 0 1 Any change on INT0 generates an interrupt request.
ATtiny26(L) Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the four sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
Note that if a level triggered external interrupt or pin change interrupt is used from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock, and if both these samples have the required level, the MCU will wake up. The period of the Watchdog Oscillator is 1.0 µs (nominal) at 3.0V and 25°C.
ATtiny26(L) Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
Timer/Counters The A Tt in y2 6/ L pr ov i de s t wo ge ne r al p ur p os e 8- b it Ti m er /Co un te rs . Th e Timer/Counters have separate prescaling selection from the separate prescaler. The Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode and an asynchronous mode. The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
ATtiny26(L) Timer/Counter1 Prescaler Figure 32 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in synchronous. The clock options are described in Table 24 on page 52 and the Timer/Counter1 Control Register, TCCR1B. Setting the PSR1 bit in TCCR1B Register resets the prescaler. The PCKE bit in the PLLCSR Register enables the asynchronous mode. Figure 32.
Figure 33. Timer/Counter0 Block Diagram Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 ($53) – – – – PSR0 CS02 CS01 CS00 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26/L and always read as zero. • Bit 3 – PSR0: Prescaler Reset Timer/Counter0 When this bit is set (one), the prescaler of the Timer/Counter0 will be reset.
ATtiny26(L) • Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0 The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0. Table 21. Clock 0 Prescale Select CS02 CS01 CS00 Description 0 0 0 Stop, the Timer/Counter0 is stopped 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T0, falling edge 1 1 1 External Pin T0, rising edge The Stop condition provides a Timer Enable/Disable function.
Figure 34.
ATtiny26(L) Figure 35. Timer/Counter1 Block Diagram CS10 CS11 CS12 CS13 CTC1 T/C CONTROL REGISTER 1 (TCCR1B) PSR1 PWM1B FOC1B PWM1A FOC1A COM1B0 COM1A0 COM1A1 TOV1 T/C CONTROL REGISTER 1 (TCCR1A) COM1B1 TOV1 OC1B (PB3) OC1B (PB2) TOV0 OCF1B OCF1A OC1A (PB1) OC1A (PB0) TIMER INT. FLAG REGISTER (TIFR) OCF1A TIMER INT.
Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $30 ($50) TCCR1A • Bits 7, 6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a Compare Match with Compare Register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A).
ATtiny26(L) • Bit 2 – FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the Compare Match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value.
• Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 24. Timer/Counter1 Prescale Select Description Asynchronous Mode Description Synchronous Mode 0 Timer/Counter1 is stopped. Timer/Counter1 is stopped.
ATtiny26(L) ware write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event. Timer/Counter1 Output Compare RegisterB – OCR1B Bit 7 6 5 4 3 2 1 0 $2C ($4C) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCR1B The Output Compare Register B is an 8-bit read/write register.
• Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
ATtiny26(L) Table 25. Compare Mode Select in PWM Mode COM1x1 COM1x0 Effect on Output Compare Pins 0 0 OC1x not connected. OC1x not connected. 0 1 OC1x cleared on compare match. Set one prescaled cycle after TCNT1 = $01. OC1x set one prescaled cycle after compare match. Cleared when TCNT1 = $00. 1 0 OC1x cleared on compare match. Set when TCNT1 = $01. OC1x not connected. 1 1 OC1x set one prescaled cycle after compare match. Cleared when TCNT = $00 OC1x not connected.
Table 26. PWM Outputs OCR1x = $00 or OCR1C, x = A or B COM1x1 COM1x0 OCR1x Output OC1x Output OC1x 0 1 $00 L H 0 1 OCR1C H L 1 0 $00 L Not connected 1 0 OCR1C H Not connected 1 1 $00 H Not connected 1 1 OCR1C L Not connected In PWM mode, the Timer Overflow Flag – TOV1, is set as in normal Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e.
ATtiny26(L) Table 27. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) Clock Selection CS13..CS10 OCR1C RESOLUTION (Bits) 20 PCK/16 0101 199 7.6 30 PCK/16 0101 132 7.1 40 PCK/8 0100 199 7.6 50 PCK/8 0100 159 7.3 60 PCK/8 0100 132 7.1 70 PCK/4 0011 228 7.8 80 PCK/4 0011 199 7.6 90 PCK/4 0011 177 7.5 100 PCK/4 0011 159 7.3 110 PCK/4 0011 144 7.2 120 PCK/4 0011 132 7.1 130 PCK/2 0010 245 7.
Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16 to 2048 ms. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
ATtiny26(L) 1. In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog. • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time is typically 8.3 ms. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready Interrupt can be set to trigger when the EEPROM is ready to accept new data. An ongoing EEPROM write operation will complete even if a reset condition occurs. In order to prevent unintentional EEPROM writes, a two state write procedure must be followed.
ATtiny26(L) • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address.
Table 29. EEPROM Programming Time Symbol EEPROM Write (from CPU) Note: Preventing EEPROM Corruption Number of Calibrated RC Oscillator Cycles(1) Typical Programming Time 8448 8.5 ms 1. Uses 1 MHz clock, independent of CKSEL-Fuse settings. During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same design solutions should be applied.
ATtiny26(L) Universal Serial Interface – USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
Register Descriptions USI Data Register – USIDR Bit 7 6 5 4 3 2 1 0 $0F ($2F) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR) the serial register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
ATtiny26(L) the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Twowire mode. A counter overflow interrupt will wakeup the processor from Idle sleep mode. • Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag.
• Bit 5..4 – USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 30. Table 30. Relations between USIWM1..
ATtiny26(L) • Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (SCK/SCL). When software strobe or Timer0 overflow clock option is selected the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option.
Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and SCK. Figure 40.
ATtiny26(L) shifted by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 41.), a bus transfer involves the following steps: 1. The slave device and master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B).
The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1<
ATtiny26(L) Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 42.
Figure 43. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D P E F Referring to the timing diagram (Figure 43.), a bus transfer involves the following steps: 1. The a start condition is generated by the master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the PORTB0 bit to zero.
ATtiny26(L) Start Condition Detector The start condition detector is shown in Figure 44. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
Analog Comparator The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher than the voltage on the negative pin PA7 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
ATtiny26(L) • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Table 33. Analog Comparator Input Selection(1) ACME ADEN MUX3...0(3) 0 X XXXX AIN1 1 1 XXXX AIN1 1 0 0000 ADC0 1 0 0001 ADC1 1 0 0010 ADC2 1 0 0011 ADC3 1 0 0100 ADC4 1 0 0101 ADC5 1 0 0110 ADC6(2) 1 0 0111 ADC7(2) 1 0 1000 ADC8 1 0 1001 ADC9 1 0 1010 ADC10 1 0 1011 Undefined 1 0 1100 Undefined 1 0 1101 Undefined 1 0 1110 Undefined 1 0 1111 Undefined Notes: 76 Analog Comparator Negative Input 1.
ATtiny26(L) Analog to Digital Converter Features • • • • • • • • • • • • • • 10-bit Resolution ±2 LSB Absolute Accuracy 0.
Figure 46. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS0 ADPS1 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSR) MUX0 MUX2 MUX1 MUX4 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS PRESCALER VCC GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC AREF SAMPLE & HOLD COMPARATOR INTERNAL 2.56 V REFERENCE 10-BIT DAC + GND INTERNAL 1.
ATtiny26(L) minal, otherwise the gain stage will saturate at 0V (GND). This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC can operate in two modes – Single Conversion and Free Running mode. In Single Conversion mode, each conversion will have to be initiated by the user. In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register.
The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency from any chip clock frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR.
ATtiny26(L) Figure 49. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 50.
ADC Noise Canceler Function The ADC features a noise canceler that enables conversion during ADC Noise Reduction mode (see “Power Management and Sleep Modes” on page 41) to reduce noise induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting.
ATtiny26(L) Figure 51. Differential Measurement Range Output Code 0x3FF 0x000 0 VREF/GAIN Differential Input Voltage (Volts) Table 35. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x3FF 1023 VADCm + 0.999 VREF /GAIN 0x3FF 1023 VADCm + 0.998 VREF /GAIN 0x3FE 1022 ... ... ... VADCm + 0.001 VREF /GAIN 0x001 1 VADCm 0x000 0 Example: ADMUX = 0xEB (ADC0 - ADC1, 20x gain, 2.
ADC Multiplexer Selection Register – ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $07 ($27) ADMUX • Bit 7, 6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 36. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).
ATtiny26(L) Table 37. Input Channel and Gain Selections MUX4..
ADC Control and Status Register – ADCSR Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 $06 ($26) ADCSR • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATtiny26(L) • Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the CK frequency and the input clock to the ADC. Table 38.
Scanning Multiple Channels Since change of analog channel always is delayed until a conversion is finished, the Free Running mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the channel shift. However, the user should take the following fact into consideration: The interrupt triggers once the result is ready to be read.
ATtiny26(L) 1 20 PA0 (ADC0) (MISO/DO/OC1A) PB1 2 19 PA1 (ADC1) (SCK/SCL/OC1B) PB2 3 18 PA2 (ADC2) (OC1B) PB3 4 17 PA3 (AREF) 5 16 VCC ATtiny26/L GND AVCC 10µΗ (MOSI/DI/SDA/OC1A) PB0 Analog Ground Plane Figure 52.
I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATtiny26(L) Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 54 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 54.
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 39 summarizes the control signals for the pin value. Table 39.
ATtiny26(L) signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 56. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 56.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATtiny26(L) Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 57 shows how the port pin control signals from the simplified Figure 54 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 57.
Table 40. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATtiny26(L) Alternate Functions of Port A Port A has an alternate functions as analog inputs for the ADC and Analog Comparator and pin change interrupt as shown in Table 41. If some Port A pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. The ADC is described in “Analog to Digital Converter” on page 77. Analog Comparator is described in “Analog Comparator” on page 74.
• ADC4, ADC3 Port – A, Bit 5, 4 ADC4/ADC3: ADC Input Channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. • AREF/PCINT1 Port – A, Bit 3 AREF: External Reference for ADC. Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference (2.
ATtiny26(L) Table 43. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AREF/PCINT1 PA2/ADC2 PA1/ADC1 PA0/ADC0 PUOE ADMUX[REFS0] 0 0 0 PUOV 0 0 0 0 DDOE ADMUX[REFS0] 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE PCINT1_ENABLE(1) • ~(2)ADMUX[REFS0] 0 0 0 DIEOV 1 0 0 0 DI PCINT1 – – – AIO ANALOG REFERENCE INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Notes: 1.
Alternate Functions Of Port B Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI programming and pin change interrupt. The ADC is described in “Analog to Digital Converter” on page 77, Clocking in “Architectural Overview” on page 6, timers in “Timer/Counters” on page 44 and USI in “Universal Serial Interface – USI” on page 63.
ATtiny26(L) PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. • ADC9/INT0/T0/PCINT1 – Port B, Bit 6 ADC9: ADC Input Channel 9.
• OC1B/PCINT0 – Port B, Bit 3 OC1B: Output Compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt.
ATtiny26(L) • DI/SDA/OC1A/PCINT0 – Port B, Bit 0 DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions., so pin must be configure as an input. SDA: Serial Data in USI Two-wire mode. Serial data pin is bi-directional and uses opencollector output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the PORTB0 or USI shiftRegister is zero when DDB0 is set (one). Pullup is disabled in USI Two-wire mode.
Table 46. Overriding Signals for Alternate Functions in PB3..
ATtiny26(L) Register Description for I/O Ports Port A Data Register – PORTA Bit Port A Data Direction Register – DDRA Port A Input Pins Address – PINA 7 6 5 4 3 2 1 0 $1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0
Memory Programming Program and Data Memory Lock Bits The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 48. The Lock bits can only be erased to “1” with the Chip Erase command. Table 47.
ATtiny26(L) Fuse Bits The ATtiny26 has two Fuse bytes. Table 49 and Table 50 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 49.
Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked.
ATtiny26(L) Figure 58. Parallel Programming +5V WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 OE PB5 RDY/BSY PB6 VCC +5V AVCC +12 V PA7: PA0 DATA RESET XTAL1/PB4 GND Table 51.
Table 53. XA1 and XA0 Coding(1) XA1 XA0 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Note: Action when XTAL1 is Pulsed 1. [XA1, XA0] = 0b11 is “No Action, Idle”. As long as XTAL1 is not pulsed, the Command, Address, and Data Registers remain unchanged. Therefore, there are no problems using BS2 as described below even though BS2 is multiplexed with XA1.
ATtiny26(L) Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5 V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least 6 times. 3. Set the Prog_enable pins listed in Table 52 on page 109 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode.
Programming the Flash The Flash is organized in pages, see Table 55 on page 110. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse.
ATtiny26(L) F. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte ($00 - $03). 4. Give XTAL1 a positive pulse. This loads the address high byte. G. Program Page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low. 3. Wait until RDY/BSY goes high. (See Figure 60 for signal waveforms.) H.
Figure 60. Programming the Flash Waveforms(1) E DATA A B $10 ADDR. LOW C D B C DATA LOW DATA HIGH ADDR. LOW DATA LOW D F DATA HIGH ADDR. HIGH G XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Note: Programming the EEPROM 1. “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 56 on page 110. When programming the EEPROM, the program data is latched into a page buffer.
ATtiny26(L) Figure 61. Programming the EEPROM Waveforms J DATA A B C B C $10 ADDR. LOW DATA ADDR. LOW DATA K XX XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 112 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. F: Load Address High Byte ($00 - $03). 3. B: Load Address Low Byte ($00 - $FF). 4. Set OE to “0”, and BS1 to “0”.
Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 112 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. Figure 62.
ATtiny26(L) Figure 63. Mapping Between BS1, BS2 and the Fuse- and Lock-bits During Read 0 Fuse Low Byte DATA 0 Lock Bits 1 BS1 Fuse High Byte 1 BS2 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte ($00 - $02). 3. Set OE to “0” and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”.
Figure 65. Parallel Programming Timing, Loading Sequenc e with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) t XLXH t XLXH LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 1. The timing requirements shown in Figure 64 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 66.
ATtiny26(L) Table 57. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
Serial Downloading Serial Programming Pin Mapping Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 58 on page 120, the pin mapping for SPI programming is listed.
ATtiny26(L) Serial Programming Algorithm When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK. When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure 68, Figure 69, and Table 69 for timing details. To program and verify the ATtiny26 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 60): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling.
ATtiny26(L) Table 60. Serial Programming Instruction Set Instruction Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 xxxx xxaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
Serial Programming Characteristics Figure 69. Serial Programming Timing MOSI tSLSH t SHOX t OVSH SCK t SHSL MISO t SLIV Table 61. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted)(1) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5 V) tCLCL tSHSL SCK Pulse Width Low tOVSH MOSI Setup to SCK High tSHOX MOSI Hold after SCK High tSLIV SCK Low to MISO Valid Note: 124 Units 8 MHz ns 0 Oscillator Period (VCC = 4.5 - 5.
ATtiny26(L) Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1.0V to VCC + 0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Power Supply Current ICC Power-down mode(6) Condition Max.
ATtiny26(L) External Clock Drive Waveforms Figure 70. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 62. External Clock Drive VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.
ADC Characteristics – Preliminary Data Table 63. ADC Characteristics Symbol Typ(1) Max(1) Condition Resolution Single Ended Conversion 10 Bits Differential Conversion Gain = 1x or 20x 8 Bits Units Single Ended Conversion VREF = 4V ADC clock = 200 kHz ADHSM = 0 1 TBD LSB Single Ended Conversion VREF = 4V ADC clock = 1 MHz ADHSM = 1 TBD TBD LSB Integral Non-linearity VREF = 4V 0.5 LSB Differential Non-linearity VREF = 4V 0.
ATtiny26(L) ATtiny26 Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 71. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 1 MHz at Vcc = 5V, T=25c) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 1.02 FRc (MHz) 1 Vcc = 5.5V Vcc = 5.0V 0.98 Vcc = 4.5V Vcc = 4.0V 0.96 Vcc = 3.6V Vcc = 3.3V 0.94 Vcc = 3.0V Vcc = 2.7V 0.92 -40 -20 0 20 40 60 80 Ta(˚C) Figure 72. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 1 MHz at Vcc = 5V, T=25c) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs.
ATtiny26(L) Figure 73. RC Oscillator Frequency vs Temperature (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 2.05 2 FRc (MHz) Vcc = 5.5V Vcc = 5.0V 1.95 Vcc = 4.5V Vcc = 4.0V 1.9 Vcc = 3.6V Vcc = 3.3V 1.85 Vcc = 3.0V Vcc = 2.7V 1.8 -40 -20 0 20 40 60 80 Ta(˚C) Figure 74. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs.
Figure 75. RC Oscillator Frequency vs Temperature (the devices are calibrated to 4 MHz at Vcc = 5V, T=25c) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.1 4.05 4 Vcc = 5.5V 3.95 Vcc = 5.0V FRc (MHz) 3.9 Vcc = 4.5V 3.85 Vcc = 4.0V 3.8 Vcc = 3.6V 3.75 Vcc = 3.3V 3.7 Vcc = 3.0V 3.65 Vcc = 2.7V 3.6 -40 -20 0 20 40 60 80 Ta(˚C) Figure 76. RC Oscillator Frequency vs.
ATtiny26(L) Figure 77. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8 MHz at Vcc = 5V, T=25c) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.4 8.2 8 Vcc = 5.5V Vcc = 5.0V FRc (MHz) 7.8 Vcc = 4.5V 7.6 Vcc = 4.0V 7.4 Vcc = 3.6V Vcc = 3.3V 7.2 Vcc = 3.0V 7 Vcc = 2.7V 6.8 -40 -20 0 20 40 60 80 Ta(˚C) Figure 78. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 8 MHz at Vcc = 5V, T=25c) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
Figure 79. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 1 MHz at Vcc = 5V, T=25c) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.03 1.02 1.01 1 Vcc = 5.5V FRc (MHz) 0.99 Vcc = 5.0V 0.98 Vcc = 4.5V 0.97 Vcc = 4.0V 0.96 Vcc = 3.6V 0.95 Vcc = 3.3V 0.94 Vcc = 3.0V 0.93 Vcc = 2.7V 0.92 -40 -20 0 20 40 60 80 Ta(˚C) Figure 80. RC Oscillator Frequency vs.
ATtiny26(L) Figure 81. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 2.05 2 FRc (MHz) Vcc = 5.5V Vcc = 5.0V 1.95 Vcc = 4.5V Vcc = 4.0V 1.9 Vcc = 3.6V Vcc = 3.3V 1.85 Vcc = 3.0V Vcc = 2.7V 1.8 -40 -20 0 20 40 60 80 Ta(˚C) Figure 82. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs.
Figure 83. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 4 MHz at Vcc = 5V, T=25c) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.1 4.05 4 Vcc = 5.5V 3.95 FRc (MHz) Vcc = 5.0V 3.9 Vcc = 4.5V 3.85 Vcc = 4.0V 3.8 Vcc = 3.6V Vcc = 3.3V 3.75 Vcc = 3.0V 3.7 Vcc = 2.7V 3.65 3.6 -40 -20 0 20 40 60 80 Ta(˚C) Figure 84. RC Oscillator Frequency vs.
ATtiny26(L) Figure 85. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8 MHz at Vcc = 5V, T=25c) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.5 8.3 8.1 FRc (MHz) 7.9 Vcc = 5.5V Vcc = 5.0V 7.7 Vcc = 4.5V Vcc = 4.0V 7.5 Vcc = 3.6V 7.3 Vcc = 3.3V 7.1 Vcc = 3.0V 6.9 Vcc = 2.7V 6.7 -40 -20 0 20 40 60 80 Ta(˚C) Figure 86. RC Oscillator Frequency vs.
ATtiny26/L Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C 18 $3E ($5E) Reserved SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 19 138 $3D ($5D) SP $3C ($5C) Reserved $3B ($5B) GIMSK - INT0 PCIE1 PCIE0 - - - - 34 $3A ($5A) GIFR - INTF0 PCIF - - - - - 35 $39 ($59) TIMSK - OCIE1A OCIE1B - - TOIE1 TOIE0 - 36 $38 ($58) TIFR - OCF1A OCF1B - - TOV1 TOV0 - 37 $37 ($57) Reserved $36
ATtiny26(L) Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 1 SBC Rd, Rr Subtract with Carry
Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags LD Rd, Y Load Indirect Rd ← (Y) None # Clocks 2 LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-inc. Rd ← (Z), Z ← Z + 1 None 2 LD Rd, -Z Load Indirect and Pre-dec.
ATtiny26(L) Ordering Information(1) Speed (MHz) Power Supply Ordering Code Package Operation Range 8 2.7 - 5.5V ATtiny26L-8PC ATtiny26L-8SC ATtiny26L-8MC 20P3 20S 32M1-A Commercial (0°C to 70°C) ATtiny26L-8PI ATtiny26L-8SI ATtiny26L-8MI 20P3 20S 32M1-A Industrial (-40°C to 85°C) ATtiny26-16PC ATtiny26-16SC ATtiny26-16MC 20P3 20S 32M1-A Commercial (0°C to 70°C) ATtiny26-16PI ATtiny26-16SI ATtiny26-16MI 20P3 20S 32M1-A Industrial (-40°C to 85°C) 16 Note: 4.5 - 5.5V 1.
Packaging Information 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.984 – E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.
ATtiny26(L) 20S 20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 0.51(0.020) 0.33(0.013) 7.60 (0.2992) 10.65 (0.419) 7.40 (0.2914) 10.00 (0.394) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 2.65 (0.1043) 2.35 (0.0926) 0.30(0.0118) 0.10 (0.0040) 0.32 (0.0125) 0.23 (0.0091) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches REV.
32M1-A D D1 PIN #1 ID 1 2 3 0 E1 E TOP VIEW A3 A2 P A1 D2 A 0.08 C PIN 1 ID SIDE VIEW 1 2 3 P COMMON DIMENSIONS (*Unit of Measure = mm) E2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A2 - 0.65 1.00 A3 b e b L BOTTOM VIEW NOTE 1. JEDEC STANDARD MO-220, Fig 2 (Anvil Singulation), VHHD-2 0.20 REF 0.18 0.23 D 5.00 BSC D1 4.75 BSC D2 2.95 3.10 E 5.00 BSC E1 4.75 BSC E2 NOTE 2.95 e 3.10 0.30 3.25 3.25 0.50 BSC L 0.30 0.40 0.50 P - - 0.
ATtiny26(L) Data Sheet Change Log for ATtiny26 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02 1. Removed all references to Power Save sleep mode in the section “System Clock and Clock Options” on page 25. 2.
ATtiny26(L) 1477B–AVR–04/02
ATtiny26(L) Table of Contents Features................................................................................................. 1 Pin Configuration.................................................................................. 2 Disclaimer ............................................................................................................. 2 Description ............................................................................................ 3 Block Diagram ..........................
Universal Serial Interface – USI......................................................... 63 Overview............................................................................................................. Register Descriptions.......................................................................................... Functional Descriptions ...................................................................................... Alternative USI Usage ........................................................
ATtiny26(L) Ordering Information(1) ..................................................................... 141 Packaging Information ..................................................................... 142 20P3 ................................................................................................................. 142 20S ................................................................................................................... 143 32M1-A ....................................................
iv ATtiny26(L) 1477B–AVR–04/02
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