Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories – 512/1024 Bytes of In-System Programmable Flash Program Memory – 32 Bytes Internal SRAM – Flash Write/Erase Cycles: 10,000 – Data Retention: 20 Years at 85oC / 100 Years at 25oC Periphe
1. Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10 SOT-23 (PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1.1 1.1.1 1 2 3 6 5 4 PB3 (RESET/PCINT3/ADC3) VCC PB2 (T0/CLKO/PCINT2/INT0/ADC2) Pin Description VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3..PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
ATtiny4/5/9/10 2. Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 2-1.
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to Digital Converter (ADC).
ATtiny4/5/9/10 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
ATtiny4/5/9/10 Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU. Figure 4-2.
ATtiny4/5/9/10 Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 7 R27 15 Y-register YL 0 7 R29 15 Z-register 0 ZL 0 R31 0 R28 ZH 7 0 R26 YH 7 0 7 0 0 R30 In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Summary” on page 151 for details). 4.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny4/5/9/10 interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.
4.8 4.8.1 Register Description CCP – Configuration Change Protection Register Bit 7 6 5 4 0x3C 3 2 1 0 CCP[7:0] CCP Read/Write W W W W W W W W Initial Value 0 0 0 0 0 0 0 0 • Bits 7:0 – CCP[7:0] – Configuration Change Protection In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles.
ATtiny4/5/9/10 The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
5. Memories This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles.
ATtiny4/5/9/10 Figure 5-1. Data Memory Map (Byte Addressing) I/O SPACE 0x0000 ... 0x003F SRAM DATA MEMORY 0x0040 ... 0x005F (reserved) 0x0060 ... 0x3EFF NVM LOCK BITS 0x3F00 ... 0x3F01 (reserved) 0x3F02 ... 0x3F3F CONFIGURATION BITS 0x3F40 ... 0x3F41 (reserved) 0x3F42 ... 0x3F7F CALIBRATION BITS 0x3F80 ... 0x3F81 (reserved) 0x3F82 ... 0x3FBF DEVICE ID BITS 0x3FC0 ... 0x3FC3 (reserved) 0x3FC4 ... 0x3FFF FLASH PROGRAM MEMORY (reserved) 5.2.1 0x4000 ... 0x41FF/0x43FF 0x4400 ...
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
ATtiny4/5/9/10 6. Clock System Figure 6-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 23. The clock systems is detailed below. Figure 6-1.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ADC is available in ATtiny5/10, only. 6.2 Clock Sources All synchronous clock signals are derived from the main clock.
ATtiny4/5/9/10 6.2.3 Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMS[1:0] bits in CLKMSR to 0b01. 6.2.4 Switching Clock Source The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 21.
6.4 6.4.1 Starting Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels.
ATtiny4/5/9/10 6.5 6.5.1 Register Description CLKMSR – Clock Main Settings Register Bit 7 6 5 4 3 2 1 0 0x37 – – – – – – CLKMS1 CLKMS0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 CLKMSR • Bit 7:2 – Res: Reserved Bits These bits are reserved and always read zero. • Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock.
6.5.3 CLKPSR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 0x36 – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 1 1 CLKPSR • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock.
ATtiny4/5/9/10 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
analog comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 81. This will reduce power consumption in idle mode. If the ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered. 7.1.
ATtiny4/5/9/10 7.3.1 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. In the powerdown mode, the analog comparator is automatically disabled. See “Analog Comparator” on page 81 for further details. 7.3.2 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
• Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0 These bits select between available sleep modes, as shown in Table 7-2. Table 7-2. Note: Sleep Mode Select SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC noise reduction (1) 0 1 0 Power-down 0 1 1 Reserved 1 0 0 Standby 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 1.
ATtiny4/5/9/10 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
8.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in section “System and Reset Characteristics” on page 119. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATtiny4/5/9/10 The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset (POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional any more. With VLM, it is possible to generate a reset at supply voltages where the MCU is still functional. When active, the VLM circuit consumes some power, as illustrated in Figure 17-48 on page 146.
Figure 8-5. Watchdog Reset During Operation CC CK 8.3 Watchdog Timer The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 86. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-2 on page 32. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs.
ATtiny4/5/9/10 Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level WDTON 8.3.1 8.3.1.
8.4 8.4.1 Register Description WDTCSR – Watchdog Timer Control and Status Register Bit 7 6 5 4 3 2 1 0 0x31 WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 – WDIF: Watchdog Timer Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
ATtiny4/5/9/10 • Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 8-3 on page 33. Table 8-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
• Bits 2:0 – VLM2:0: Trigger Level of Voltage Level Monitor These bits set the trigger level for the voltage level monitor, as described in Table 8-4 below. Table 8-4. Setting the Trigger Level of Voltage Level Monitor. VLM2:0 Label Description 000 VLM0 Voltage Level Monitor disabled 001 VLM1L 010 VLM1H Triggering generates a regular Power-On Reset (POR).
ATtiny4/5/9/10 9. Interrupts This section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 10. 9.1 Interrupt Vectors Interrupt vectors of ATtiny4/5/9/10 are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
9.2 0x000B RESET: ldi r16, high(RAMEND); Main program start 0x000C out SPH,r16 0x000D ldi r16, low(RAMEND) ; to top of RAM 0x000E out SPL,r16 0x000F sei 0x0010 ... ... ; Set Stack Pointer ; Enable interrupts External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins are configured as outputs.
ATtiny4/5/9/10 Figure 9-1. Timing of pin change interrupts pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_syn pcint_setflag PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 9.3 9.3.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 9-2. 9.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
ATtiny4/5/9/10 9.3.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 0x12 – – – – – – – PCIE0 Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..
10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors. Each output buffer has symmetrical drive characteristics with both high sink and source capability.
ATtiny4/5/9/10 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) REx Q D PUExn Q CLR RESET Q WEx D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx SLEEP WPx RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O SLEEP: clk I/O : Note: 10.2.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). The pull-up resistor is activated, if the PUExn is written logic one.
ATtiny4/5/9/10 Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK r16 0x02 r17 0x01 INSTRUCTIONS out DDRx, r16 nop PORTx DDRx 0x55 0x02 0x01 Px0 Px1 out DDRx, r17 0x01 tri-state tri-state tri-state intermediate tri-state cycle 10.2.4 intermediate tri-state cycle Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5 on page 44. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-5. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 10.2.
ATtiny4/5/9/10 10.2.7 Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example ...
Figure 10-6.
ATtiny4/5/9/10 Table 10-2 on page 47 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-6 on page 46 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3 on page 48. Table 10-3.
ATtiny4/5/9/10 • OC0B: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. • PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change interrupt 0. • TPICLK: Serial Programming Clock.
Table 10-5. Signal Name PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1 PUOE EXT_CLOCK 0 PUOV 0 0 DDOE EXT_CLOCK(1) 0 DDOV 0 0 EXT_CLOCK (1) + OC0B Enable OC0A Enable (1) • OC0B OC0A PVOV EXT_CLOCK PTOE 0 0 (1) + (PCINT1 • PCIE0) + DIEOE EXT_CLOCK ADC1D DIEOV (EXT_CLOCK(1) • PWR_DOWN) + (EXT_CLOCK(1) • PCINT1 • PCIE0) PCINT0 • PCIE0 DI CLOCK/ICP0/PCINT1 Input PCINT0 Input AIO ADC1/Analog Comparator Negative Input ADC0/Analog Comparator Positive Input Notes: 10.4.
ATtiny4/5/9/10 10.4.3 10.4.4 10.4.
11. 16-bit Timer/Counter0 11.1 Features • • • • • • • • • • • 11.
ATtiny4/5/9/10 A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 11-1 on page 52. For actual placement of I/O pins, refer to “Pinout of ATtiny4/5/9/10” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 73. Most register and bit references in this section are written in general form.
11.3 Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter control Register B (TCCR0B). For details on clock sources and prescaler, see section “Prescaler”. 11.3.1 Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1).
ATtiny4/5/9/10 clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 11.3.2 External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic.
Figure 11-4. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction TCNTn (16-bit Counter) Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Direction Clear clkT0 TOP BOTTOM Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock. Signalize that TCNT0 has reached maximum value.
ATtiny4/5/9/10 11.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP0 pin. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
tion mode (WGM03:0) bits must be set before the TOP value can be written to the ICR0 Register. When writing the ICR0 Register the high byte must be written to the ICR0H I/O location before the low byte is written to ICR0L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 71. 11.5.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP0).
ATtiny4/5/9/10 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF0 flag is not required (if an interrupt handler is used). 11.6 Output Compare Units The 16-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0x). If TCNT equals OCR0x the comparator signals a match. A match will set the Output Compare Flag (OCF0x) at the next timer clock cycle.
double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.
ATtiny4/5/9/10 11.7 Compare Match Output Unit The Compare Output Mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match. Secondly the COM0x1:0 bits control the OC0x pin output source. Figure 11-7 on page 61 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
11.7.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 74. For fast PWM mode refer to Table 11-3 on page 74, and for phase correct and phase and frequency correct PWM refer to Table 11-4 on page 74.
ATtiny4/5/9/10 The timing diagram for the CTC mode is shown in Figure 11-8 on page 63. The counter value (TCNT0) increases until a compare match occurs with either OCR0A or ICR0, and then counter (TCNT0) is cleared. Figure 11-8.
operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A.
ATtiny4/5/9/10 The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0 Register is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR0 value written is lower than the current value of TCNT0. The result will then be that the counter will miss the compare match at the TOP value.
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX).
ATtiny4/5/9/10 Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR0x Registers are written. As the third period shown in Figure 11-10 on page 66 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR0x Register.
the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR0 (WGM03:0 = 8), or the value in OCR0A (WGM03:0 = 9). The counter has then reached the TOP and changes the count direction.
ATtiny4/5/9/10 Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR0A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins.
Figure 11-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 11-14 on page 70 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATtiny4/5/9/10 Figure 11-15. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 11.10 Accessing 16-bit Registers The TCNT0, OCR0A/B, and ICR0 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
Assembly Code Example ... ; Set TCNT0 to 0x01FF r17,0x01 r16,0xFF TCNT0H,r17 TCNT0L,r16 ; Read TCNT0 into r17:r16 r16,TCNT0L r17,TCNT0H ... Note: See “Code Examples” on page 5. The code example returns the TCNT0 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations.
ATtiny4/5/9/10 Assembly Code Example TIM16_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret Note: See “Code Examples” on page 5. The code example requires that the r17:r16 register pair contains the value to be written to TCNT0. 11.10.
When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on the WGM03:0 bits. Table 11-2 shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to a Normal or CTC (non-PWM) Mode. Table 11-2.
ATtiny4/5/9/10 • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform to generate. See Table 11-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 62). Table 11-5. 11.11.
When a capture is triggered according to the ICES0 setting, the counter value is copied into the Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in the TCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Capture function is disabled.
ATtiny4/5/9/10 The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that determine the effect of the forced compare. A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR0A as TOP. The FOC0A/FOC0B bits are always read as zero. • Bits 5:0 – Reserved Bits These bits are reserved for future use.
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16bit registers. See “Accessing 16-bit Registers” on page 71. 11.11.
ATtiny4/5/9/10 11.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0 Bit 7 6 5 4 3 2 1 0 0x2A – – ICF0 – – OCF0B OCF0A TOV0 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7:6, 4:3 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written.
This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
ATtiny4/5/9/10 12. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATtiny4/5/9/10 13. Analog to Digital Converter 13.1 Features • • • • • • • • • • • • 13.2 8-bit Resolution 0.5 LSB Integral Non-linearity ± 1 LSB Absolute Accuracy 65µs Conversion Time 15 kSPS at Full Resolution Four Multiplexed Single Ended Input Channels Input Voltage Range: 0 – VCC Supply Voltage Range: 2.5V – 5.
Figure 13-1. Analog to Digital Converter Block Schematic ADCSRB ADCL ADIE ADEN ADPS0 ADPS1 ADPS2 ADSC ADATE ADCSRA ADTS2:0 ADC IRQ TRIGGER SELECT PRESCALER ADIF CHANNEL START DECODER ADC7:0 MUX1 MUX0 ADMUX INTERRUPT FLAGS 8-BIT DATA BUS CONVERSION LOGIC VREF VCC 8-BIT DAC + ADC3 ADC2 ADC1 INPUT MUX SAMPLE & HOLD COMPARATOR ADC0 13.
ATtiny4/5/9/10 Figure 13-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC data register. The first conversion must be started by writing a logical one to bit ADSC bit in ADCSRA.
switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles, as summarised in Table 13-1 on page 87.
ATtiny4/5/9/10 Figure 13-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCL Conversion Result Prescaler MUX Reset Update Conversion Prescaler Reset Complete Sample & Hold In Free Running mode (see Figure 13-7), a new conversion will be started immediately after the conversion completes, while ADSC remains high. Figure 13-7.
13.6 Changing Channel The MUXn bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channel selection only takes place at a safe point during the conversion. The channel is continuously updated until a conversion is started. Once the conversion starts, the channel selection is locked to ensure a sufficient sampling time for the ADC.
ATtiny4/5/9/10 • Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. • Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. • If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
13.9 Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by applying the following techniques: • Keep analog signal paths as short as possible. • Make sure analog tracks run over the analog ground plane. • Keep analog tracks well away from high-speed switching digital tracks.
ATtiny4/5/9/10 • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 13-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 13-12. Differential Non-linearity (DNL) Output Code 0xFF 1 LSB DNL 0x00 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
ATtiny4/5/9/10 13.12 Register Description 13.12.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 0x1B – – – – – – MUX1 MUX0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 13-2 for details.
• Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
ATtiny4/5/9/10 trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 13-4. 13.12.
14. Programming interface 14.
ATtiny4/5/9/10 The TPI is accessed via three pins, as follows: RESET: TPICLK: TPIDATA: Tiny Programming Interface enable input Tiny Programming Interface clock input Tiny Programming Interface data input/output In addition, the VCC and GND pins must be connected between the external programmer and the device. See Figure 14-2. Figure 14-2.
14.3.2 Disabling Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inactive high state or, alternatively, if VHV is no longer applied to the RESET pin. If the NVM enable bit is not cleared a power down is required to exit TPI programming mode. See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 106. 14.3.3 Frame Format The TPI physical layer supports a fixed frame format.
ATtiny4/5/9/10 14.3.6 Operation The TPI physical layer operates synchronously on the TPICLK provided by the external programmer. The dependency between the clock edges and data sampling or data change is shown in Figure 14-6. Data is changed at falling edges and sampled at rising edges. Figure 14-6. Data changing and Data sampling. TPICLK TPIDATA SAMPLE SETUP The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive mode, waiting for a start bit.
14.3.9 Collision Detection Exception The TPI physical layer uses one bi-directional data line for both data reception and transmission. A possible drive contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a collision detection mechanism is supported. The collision detection is based on the way the TPI physical layer drives the TPIDATA line.
ATtiny4/5/9/10 The TPI access layer controls the character transfer direction on the TPI physical layer. It also handles the recovery from the error state after exception. The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control and status registers in the TPI access Layer. The CSS consist of registers directly involved in the operation of the TPI itself. These register are accessible using the SLDCS and SSTCS instructions.
14.5 Instruction Set The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data space. The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte operand following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized. The TPI instruction set is summarised in Table 14-1. Table 14-1. 14.5.
ATtiny4/5/9/10 14.5.2 SST - Serial STore to data space using indirect addressing The SST instruction uses indirect addressing to store into data space the byte that is shifted into the physical layer shift register. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before the operation. The Pointer Register can be either left unchanged by the operation, or it can be post-incremented, as shown in Table 14-3. Table 14-3. 14.5.
14.5.6 SLDCS - Serial LoaD data from Control and Status space using direct addressing The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physical layer shift register for serial read-out. The SLDCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction, as shown in Table 14-7. Table 14-7. 14.5.
ATtiny4/5/9/10 14.7 Control and Status Space Register Descriptions The control and status registers of the Tiny Programming Interface are mapped in the Control and Status Space (CSS) of the interface. These registers are not part of the I/O register map and are accessible via SLDCS and SSTCS instructions, only. The control and status registers are directly involved in configuration and status monitoring of the TPI. A summary of CSS registers is shown in Table 14-11. Table 14-11.
• Bits 2:0 – GT[2:0]: Guard Time These bits specify the number of additional IDLE bits that are inserted to the idle time when changing from reception mode to transmission mode. Additional delays are not inserted when changing from transmission mode to reception. The total idle time when changing from reception to transmission mode is Guard Time plus two IDLE bits. Table 14-13 shows the available Guard Time settings. Table 14-13.
ATtiny4/5/9/10 15. Memory Programming 15.1 Features • Two Embedded Non-Volatile Memories: • • • • • 15.
15.3 Non-Volatile Memories The ATtiny4/5/9/10 have the following, embedded NVM: • Non-Volatile Memory Lock Bits • Flash memory with four separate sections 15.3.1 Non-Volatile Memory Lock Bits The ATtiny4/5/9/10 provide two Lock Bits, as shown in Table 15-1. Table 15-1.
ATtiny4/5/9/10 15.3.2 Flash Memory The embedded Flash memory of ATtiny4/5/9/10 has four separate sections, as shown in Table 15-3 and Table 15-3. Table 15-3. Number of Words and Pages in the Flash (ATtiny9/10) Section Size (Bytes) Page Size (Words) Pages WADDR PADDR 1024 8 64 [3:1] [9:4] Configuration 8 8 1 [3:1] – Signature (1) 16 8 2 [3:1] [4:4] 8 8 1 [3:1] – Code (program memory) Calibration Notes: (1) 1. This section is read-only. Table 15-4.
Configuration bits are not affected by a chip erase but they can be cleared using the configuration section erase command (see “Erasing the Configuration Section” on page 113). Note that configuration bits are locked if Non-Volatile Lock Bit 1 (NVLB1) is programmed. 15.3.3.1 15.3.4 Latching of Configuration Bits All configuration bits are latched either when the device is reset or when the device exits the external programming mode.
ATtiny4/5/9/10 15.3.5.1 15.4 Latching of Calibration Value To ensure correct frequency of the calibrated internal oscillator the calibration value is automatically written into the OSCCAL register during reset. Accessing the NVM NVM lock bits, and all Flash memory sections are mapped to the data space as shown in Figure 5-1 on page 15. The NVM can be accessed for read and programming via the locations mapped in the data space.
Figure 15-1. Addressing the Flash Memory 16 PADDRMSB WADDRMSB+1 WADDRMSB PADDR WADDR 1 0/1 ADDRESS POINTER LOW/HIGH BYTE SELECT FLASH SECTION FLASH PAGE 00 00 01 01 02 ... ... ... PAGE PAGE ADDRESS WITHIN A FLASH SECTION WORD WORD ADDRESS WITHIN A FLASH PAGE ... ... ... PAGEEND SECTIONEND 15.4.2 Reading the Flash The Flash can be read from the data memory mapped locations one byte at a time.
ATtiny4/5/9/10 Before starting the Chip erase, the NVMCMD register must be loaded with the CHIP_ERASE command. To start the erase operation a dummy byte must be written into the high byte of a word location that resides inside the Flash code section. The NVMBSY bit remains set until erasing has been completed. While the Flash is being erased neither Flash buffer loading nor Flash reading can be performed. The Chip Erase can be carried out as follows: 1. Write the CHIP_ERASE command to the NVMCMD register 2.
15.4.4 Reading NVM Lock Bits The Non-Volatile Memory Lock Byte can be read from the mapped location in data memory. 15.4.5 Writing NVM Lock Bits The algorithm for writing the Lock bits is as follows. 1. Write the WORD_WRITE command to the NVMCMD register. 2. Write the lock bits value to the Non-Volatile Memory Lock Byte location. This is the low byte of the Non-Volatile Memory Lock Word. 3. Start the NVM Lock Bit write operation by writing a dummy byte to the high byte of the NVM Lock Word location. 4.
ATtiny4/5/9/10 15.7 15.7.1 Register Description NVMCSR - Non-Volatile Memory Control and Status Register Bit 7 6 5 4 3 2 1 NVMBSY – – – – – – – Read/Write R/W R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0x32 0 NVMCSR • Bit 7 - NVMBSY: Non-Volatile Memory Busy This bit indicates the NVM memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed.
16. Electrical Characteristics 16.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATtiny4/5/9/10 DC Characteristics. TA = -40°C to +85°C (1) (Continued) Table 16-1. Symbol Parameter Condition Power Supply Current ICC Power-down mode Notes: Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.33 0.8 mA Active 4MHz, VCC = 3V 1.6 2.5 mA Active 8MHz, VCC = 5V 5 9 mA Idle 1MHz, VCC = 2V 0.11 0.4 mA Idle 4MHz, VCC = 3V 0.4 1.0 mA Idle 8MHz, VCC = 5V 1.5 3.5 mA WDT enabled, VCC = 3V 4.5 10 µA WDT disabled, VCC = 3V 0.15 2 µA 1.
16.4 Clock Characteristics 16.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 17-39 on page 142 and Figure 17-40 on page 142. Table 16-2.
ATtiny4/5/9/10 16.5 System and Reset Characteristics Table 16-4. Symbol Parameter Condition Min(1) Typ(1) VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin tTOUT Time-out after reset 64 VHYST VLM Hysteresis 50 Note: 16.5.1 Reset, VLM, and Internal Voltage Characteristics 0.2 VCC VCC = 1.8V VCC = 3V VCC = 5V Max(1) Units 0.9VCC V 2000 700 400 ns 128 ms mV 1. Values are guidelines, only Power-On Reset Table 16-5.
16.6 Analog Comparator Characteristics Table 16-7. Analog Comparator Characteristics, TA = -40°C - 85°C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.
ATtiny4/5/9/10 16.8 Serial Programming Characteristics Figure 16-3. Serial Programming Timing Receive Mode Transmit Mode TPIDATA tIVCH tCHIX tCLOV TPICLK tCLCH tCHCL tCLCL Table 16-9.
17. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
ATtiny4/5/9/10 17.2 17.2.1 ATtiny4/5/9/10 Active Supply Current Figure 17-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.7 5.5 V 0.6 5.0 V 0.5 4.5 V ICC (mA) 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 17-2. Active Supply Current vs. frequency (1 - 12 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 4.
Figure 17-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 3.5 -40 °C 25 °C 85 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 1 0.9 -40 °C 25 °C 85 °C 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny4/5/9/10 Figure 17-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 KHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-6. Active Supply Current vs. VCC (External Clock, 32 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 32 KHz 0.04 -40 °C 85 °C 25 °C 0.035 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
17.2.2 Idle Supply Current Figure 17-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.07 5.5 V 0.06 5.0 V 0.05 ICC (mA) 4.5 V 0.04 4.0 V 0.03 3.3 V 2.7 V 0.02 1.8 V 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 17-8. Idle Supply Current vs. Frequency (1 - 12 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 0.8 5.5 V 0.7 5.0 V 0.6 4.5 V ICC (mA) 0.5 0.4 4.0 V 0.3 3.3 V 0.2 2.7 V 0.1 1.
ATtiny4/5/9/10 Figure 17-9. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 0.5 85 °C 25 °C -40 °C 0.45 0.4 0.35 ICC (mA) 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-10. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 0.3 85 °C 25 °C -40 °C 0.25 ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
17.2.3 Power-down Supply Current Figure 17-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0.5 85 °C 0.45 0.4 0.35 ICC (uA) 0.3 0.25 0.2 0.15 25 °C 0.1 -40 °C 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 9 -40 °C 8 25 °C 85 °C 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.
ATtiny4/5/9/10 17.2.4 Pin Pull-up Figure 17-13. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 17-14. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 20 10 25 °C 85 °C -40 °C 0 0 0.5 1 1.5 2 2.
Figure 17-15. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 160 140 120 IOP (uA) 100 80 60 40 20 25 °C 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 17-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 45 40 35 IRESET (uA) 30 25 20 15 10 -40 °C 5 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATtiny4/5/9/10 Figure 17-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 70 60 IRESET (uA) 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 17-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
17.2.5 Pin Driver Strength Figure 17-19. I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.8 0.7 85 °C 0.6 VOL (V) 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL (mA) Figure 17-20. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.8 0.7 85 °C 0.6 VOL (V) 0.5 25 °C -40 °C 0.4 0.3 0.2 0.
ATtiny4/5/9/10 Figure 17-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 85 °C 0.8 -40 °C 25 °C VOL (V) 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 17-22. I/O Pin Output Voltage vs. Source Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 2 1.8 1.6 VOH (V) 1.4 1.2 -40 °C 1 25 °C 0.8 85 °C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 17-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.1 2.9 VOH (V) 2.7 2.5 -40 °C 25 °C 2.3 85 °C 2.1 1.9 1.7 1.5 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 17-24. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5.2 5 VOH (V) 4.8 4.6 4.4 -40 °C 25 °C 4.
ATtiny4/5/9/10 Figure 17-25. Reset Pin as I/O, Output Voltage vs. Sink Current OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 1 3.0 V 1.8 V 0.9 0.8 0.7 5.0 V VOL (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IOL (mA) Figure 17-26. Reset Pin as I/O, Output Voltage vs. Source Current OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 VOH (V) 3 5.0 V 2 1 3.0 V 1.8 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
17.2.6 Pin Threshold and Hysteresis Figure 17-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 3.5 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-28. I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.
ATtiny4/5/9/10 Figure 17-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 Input Hysteresis (V) 0.5 25 °C 85 °C -40 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-30. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIH, RESET READ AS '1' 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-31. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-32. Reset Pin, Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 Input Hysteresis (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny4/5/9/10 Figure 17-33. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, I/O PIN READ AS '1' 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-34. Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-35. Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O) RESET PIN AS I/O, INPUT HYSTERESIS vs. VCC VIL, PIN READ AS "0" 1 0.9 Input Hysteresis (mV) 0.8 85 °C 25 °C -40 °C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 17.2.7 Analog Comparator Offset Figure 17-36.
ATtiny4/5/9/10 17.2.8 Internal Oscillator Speed Figure 17-37. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 Frequency (kHz) 107 -40 °C 106 105 25 °C 104 103 102 101 85 °C 100 99 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-38. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 110 109 108 Frequency (kHz) 107 106 105 104 1.8 V 103 2.7 V 102 3.3 V 101 4.0 V 5.
Figure 17-39. Calibrated Oscillator Frequency vs. VCC CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.4 -40 °C 8.2 Frequency (MHz) 25 °C 85 °C 8 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-40. Calibrated Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 Frequency (MHz) 8.1 8 7.9 5.0 V 7.8 3.0 V 7.7 1.8 V 7.
ATtiny4/5/9/10 Figure 17-41. Calibrated Oscillator Frequency vs, OSCCAL Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE VCC = 3V 16 25 °C 85 °C -40 °C 14 Frequency (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 17.2.9 VLM Thresholds Figure 17-42. VLM1L Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 001 1.42 1.41 Threshold (V) 1.4 1.39 1.38 1.37 1.36 1.35 1.
Figure 17-43. VLM1H Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 010 1.7 Threshold (V) 1.65 1.6 1.55 1.5 1.45 1.4 -40 -20 0 20 40 60 80 100 60 80 100 Temperature (C) Figure 17-44. VLM2 Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 011 2.48 Threshold (V) 2.47 2.46 2.45 2.44 2.
ATtiny4/5/9/10 Figure 17-45. VLM3 Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 100 3.9 Threshold (V) 3.8 3.7 3.6 3.5 3.4 -40 -20 0 20 40 60 80 100 Temperature (C) 17.2.10 Current Consumption of Peripheral Units Figure 17-46. ADC Current vs. VCC (ATtiny5/10, only) ADC CURRENT vs. VCC 4.0 MHz FREQUENCY 700 600 ICC (uA) 500 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-47. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 140 120 ICC (uA) 100 25 ˚C 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-48. VCC Level Monitor Current vs. VCC VLM SUPPLY CURRENT vs. VCC 0.35 0.3 VLM2:0 = 001 VLM2:0 = 010 VLM2:0 = 011 0.25 ICC (mA) VLM2:0 = 100 0.2 0.15 0.1 0.05 0 VLM2:0 = 000 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny4/5/9/10 Figure 17-49. Temperature Dependence of VLM Current vs. VCC VLM SUPPLY CURRENT vs. VCC VLM2:0 = 001 350 -40 °C 300 25 °C 85 °C ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-50. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs.
17.2.11 Current Consumption in Reset and Reset Pulsewidth Figure 17-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.08 5.5 V 0.07 5.0 V 0.06 4.5 V ICC (mA) 0.05 4.0 V 0.04 3.3 V 0.03 2.7 V 0.02 1.8 V 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 17-52. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
ATtiny4/5/9/10 18.
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
ATtiny4/5/9/10 19.
Mnemonics Operands Description Operation Flags #Clocks BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ
ATtiny4/5/9/10 20. Ordering Information 20.1 ATtiny4 Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range 12 1.8 - 5.5V ATtiny4-TSHR 6ST1 Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
20.2 ATtiny5 Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range 12 1.8 - 5.5V ATtiny5-TSHR 6ST1 Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 6ST1 154 6-lead, 2.90 x 1.
ATtiny4/5/9/10 20.3 ATtiny9 Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range 12 1.8 - 5.5V ATtiny9-TSHR 6ST1 Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 6ST1 6-lead, 2.
20.4 ATtiny10 Speed (MHz) Power Supply Ordering Code(1) Package(2) Operational Range 12 1.8 - 5.5V ATtiny10-TSHR 6ST1 Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 6ST1 156 6-lead, 2.90 x 1.
ATtiny4/5/9/10 21. Packaging Information 21.1 6ST1 D 5 6 E E1 A 4 A2 Pin #1 ID b A1 3 2 0.10 C SEATING PLANE A 1 A C Side View e Top View A2 A 0.10 C SEATING PLANE c 0.25 O C A1 C View A-A SEATING PLANE SEE VIEW B L View B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does not include mold Flash, protrusions or gate burrs.
22. Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 22.1 22.1.1 ATtiny4 Rev. C No known errata. 22.1.2 Rev. A – B Not sampled. 22.2 22.2.1 ATtiny5 Rev. C No known errata. 22.2.2 Rev. A – B Not sampled. 22.3 22.3.1 ATtiny9 Rev. C No known errata. 22.3.2 Rev. A – B Not sampled. 22.4 ATtiny10 22.4.1 Rev. C No known errata. 22.4.2 Rev. A – B Not sampled.
ATtiny4/5/9/10 23. Datasheet Revision History 23.1 Rev. 8127B – 08/09 1. Updated document template 2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9 3. Added section: – “Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 4 4.
ATtiny4/5/9/10 8127B–AVR–08/09
ATtiny4/5/9/10 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 3 2.1 3 4 5 6 7 Pin Description ..................................................................................................
8 9 7.3 Minimizing Power Consumption ......................................................................24 7.4 Register Description ........................................................................................25 System Control and Reset .................................................................... 27 8.1 Resetting the AVR ...........................................................................................27 8.2 Reset Sources ..............................................
ATtiny4/5/9/10 13.4 Starting a Conversion ......................................................................................84 13.5 Prescaling and Conversion Timing ..................................................................85 13.6 Changing Channel ...........................................................................................88 13.7 ADC Noise Canceler .......................................................................................88 13.8 Analog Input Circuitry .......
17.1 Supply Current of I/O Modules ......................................................................122 17.2 ATtiny4/5/9/10 ...............................................................................................123 18 Register Summary ............................................................................... 149 19 Instruction Set Summary .................................................................... 151 20 Ordering Information ....................................................
ATtiny4/5/9/10 v 8127B–AVR–08/09
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