Manual

7
4890AS–GPS–09/05
ATR0621 [Preliminary]
P6 A8 I/O OH NOE/NRD NOE/NRD “0”
P7 D2 I/O OH NUB/NWR1 NUB/NWR1 “0”
P8 G2 I/O STATUSLED “0”
P9 J8 I/O PU EXTINT0 EXTINT0
P10 E4 I/O OH EM_A0/NLB EM_A0/NLB “0”
P11 H10 I/O OH EM_A21 NCS2 EM_A21
P12 F3 I/O Configurable (PU) GPSMODE2 NPCS2
P13 G10 I/O PU GPSMODE3 EXTINT1
P14 J5 I/O Configurable (PD) NAADET1 “0”
P15 K5 I/O PD ANTON
P16 E1 I/O Configurable (PU) NEEPROM SIGHI1 NWD_OVF
P17 J4 I/O Configurable (PD) GPSMODE5 SCK1 SCK1
P18 K4 I/O Configurable (PU) TXD1 TXD1 “0”
P19 F1 I/O Configurable (PU) GPSMODE6 SIGLO1 “0”
P20 H2 I/O Configurable (PU) TIMEPULSE SCK2 SCK2 TIMEPULSE
P21 F2 I/O Configurable (PU) TXD2 TXD2 “0”
P22 H8 I/O PU RXD2 RXD2
P23 H3 I/O Configurable (PU) GPSMODE7 SCK SCK MCLK_OUT
P24 H1 I/O Configurable (PU) GPSMODE8 MOSI MOSI “0”
P25 D1 I/O Configurable (PU) NAADET0 MISO MISO “0”
P26 G8 I/O Configurable (PU) GPSMODE10 NSS NPCS0 “0”
P27 E2 I/O Configurable (PU) GPSMODE11 NPCS1
P28 G1 I/O OH EM_A20 NCS3 EM_A20
P29 E3 I/O Configurable (PU) GPSMODE12 NPCS3
P30 G5 I/O PD AGCOUT0 AGCOUT0 “0”
P31 H9 I/O PU RXD1 RXD1
RF_ON K6 OUT PD
SIGHI0 F9 OUT
SIGLO0 E10 OUT
TCK J3 IN PU
TDI J2 IN PU
TDO K3 OUT
TMS J1 IN PU
USB_DM F10 I/O
USB_DP D3 I/O
VBAT J7 IN
Table 3-1. ATR0621 Pinout (Continued)
Pin Name LFBGA100 Pin Type
Pull Resistor
(Reset Value)
(1)
Firmware Label PIO Bank A PIO Bank B
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.