User Manual

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Features

•

Utilizes the ARM7TDMI

™

ARM

Thumb

Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Embedded ICE (In-circuit Emulation)

•

128 Kbytes Internal RAM

•

Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 64 MB

– Up to Four Chip Selects

– Software Programmable 8-/16-bit External Data Bus

•

16-channel GPS Correlator

– Accuracy: TBD

– Time to First Fix: TBD

•

8-channel Peripheral Data Controller (PDC)

•

8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Three External Interrupts

•

20 Programmable I/O Lines

•

Three USARTs

– Two Dedicated Peripheral Data Controller (PDC) Channels per USART

•

Master/Slave SPI Interface

– Two Dedicated Peripheral Data Controller (PDC) Channels

– 8- to 16-bit Programmable Data Length

– Four External Slave Chip Selects

•

Programmable Watchdog Timer

•

Power Management Controller (PMC)

– CPU and Peripherals Can Be Deactivated Individually

•

Clock Manager (CLM)

– Geared Master Clock to Reduce Power Consumption

– Sleep State with Disabled Master Clock

•

PWM Controller

– Two PWM Signals

•

Real Time Clock (RTC)

– Time in GPS Format and 15-bit Fractional Part of a Second

– Programmable Interrupt

– Timer with a 8-bit Fractional Part of a Second and Parallel Load

•

2.3V to 3.6V or 1.8V Supply Voltage

•

Includes Power Supervisor

•

Battery Backup Memory

•

9 mm × 9 mm 100-pin BGA Package

GPS Baseband

Processor

ATR0620

Summary

Preliminary

Rev. 4574CS–GPS–05/05

Summary of content (15 pages)

PAGE 1
Features • Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core • • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Embedded ICE (In-circuit Emulation) 128 Kbytes Internal RAM Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 64 MB – Up to Four Chip Selects – Software Programmable 8-/16-bit External Data Bus 16-channel GPS Correlator – Accuracy: TBD – Time to First Fix: TBD 8-channel Peripheral Data Contr
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1. Description The GPS baseband processor ATR0620 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications.
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ATR0620 [Preliminary] Block Diagram GPS Correlators RTC SRAM nSHDN nSLEEP Power Management Controller CLK32768 PIO2 GPS Accelerator Figure 1-1.
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Table 1-1.
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ATR0620 [Preliminary] Table 1-1.
PAGE 6
Table 1-1.
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ATR0620 [Preliminary] Table 1-1. Pin Configuration (Continued) PIO Bank A PIO Bank B Serial Number BGA 100 CPGA 144 Pin Name Firmware Label I O I O 138 (1) A7 TMON21 (1) (1) (1) (1) (1) 139 (1) B6 TMON22 (1) (1) (1) (1) (1) 140 (1) Q5 TMON23 (1) (1) (1) (1) (1) 141 (1) Q4 TMON24 (1) (1) (1) (1) (1) 142 (1) N5 TMON25 (1) (1) (1) (1) (1) 143 (1) P3 TMON26 (1) (1) (1) (1) (1) (1) K14 POR_VEXT (1) (1) (1) (1) (1) 144 Note: 1.
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Table 1-2.
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ATR0620 [Preliminary] 2. Architecture Overview The ATR0620 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption.
PAGE 10
4. EBI: External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64 bytes. It has four chip selects and a 20-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing single clock cycle memory accesses.
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ATR0620 [Preliminary] 7. USART2: Universal Synchronous/ Asynchronous Receiver/Transmitter The ATR0620 provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the peripheral data controller.
PAGE 12
. SF: Special Function The ATR0620 provides registers that implement the following special functions: • Chip identification • RESET status 13. PWM The PWM includes two PWM channels. They can be programmed separately. It is possible to generate an output voltage range from 0 to (255/256) × VDD18. 14. RTC The RTC provides the time in GPS format. The structure of the GPS system time: zero point is midnight Universal Time (UT) 5th/6th of January 1980.
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ATR0620 [Preliminary] 17. Ordering Information Extended Type Number Package ATR0620-100 CTBGA100 ATR0620-144 CPGA144 Remarks 9 mm × 9 mm, 0.80 mm pitch Debug package 18. Package Outline CTBGA100 TOP VIEW SIDE VIEW 1.10 ± 0.10 0.30 ± 0.05 9.00 ± 0.05 9.00 ± 0.05 0.40 Dia. TYP 0.60 ± 0.05 0.80 ± 0.05 BOTTOM VIEW A1 BALL PAD CORNER 10 9 8 7 6 5 4 3 2 1 A B C D 0.90 ± 0.05 E F G H J K 0.90 ± 0.05 0.80 ± 0.
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19. Package CPGA144 TOP VIEW SIDE VIEW 0.090 ± 0.009 1.575 ± 0.16 1.575 ± 0.16 0.018 ± 0.002 BOTTOM VIEW 1.400 ± 0.012 0.
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.