Owner manual

92
ATmega8515(L)
2512A–AVR–04/02
Timer/Counter0 and
Timer/Counter1
Prescalers
Timer/Counter1and Timer/Counter0 sharethe same prescaler module,but the
Timer/Counters can have different prescalersettings.The description below applies to
both Timer/Counter1and Timer/Counter0.
Internal Clock Source TheTimer/Countercan be clockeddirectly by the system clock (by setting the
CSn2:0 = 1).Thisprovides the fastestoperation,with amaximum Timer/Counterclock
frequency equal to system clock frequency (f
CLK_I/O
).Alternatively, one offour taps from
the prescalercan beused as a clock source. The prescaledclock has a frequency of
eitherf
CLK_I/O
/8,f
CLK_I/O
/64,f
CLK_I/O
/256, orf
CLK_I/O
/1024.
Prescaler Reset The prescaler isfree running, i.e., operates independently of the clock select logic of the
Timer/Counter, and it issharedbyTimer/Counter1and Timer/Counter0. Sincethe pres-
caler is not affectedbytheTimer/Counter’sclock select, the state of the prescalerwill
have implicationsforsituationswhereaprescaledclock is used. One exampleofpres-
caling artifacts occurs when thetimer is enabled andclockedbythe prescaler
(6 > CSn2:0 > 1).The number ofsystem clock cyclesfrom when thetimer is enabled to
the first count occurs can be from 1 to N+1 system clock cycles, where N equals the
prescalerdivisor(8,64, 256, or 1024).
ItispossibletousethePrescaler Reset forsynchronizing theTimer/Counter to program
execution. However, caremust betaken if theother Timer/Counter that shares the
same prescaler alsousesprescaling. A Prescaler Reset will affectthe prescalerperiod
for all Timer/Counters it isconnected to.
External Clock Source An externalclock sourceapplied to theT1/T0pin can beused as Timer/Counterclock
(clk
T1
/clk
T0
).TheT1/T0pin issampled onceevery system clock cycle by the pin syn-
chronization logic.The synchronized(sampled) signal is then passed through theedge
detector. Figure44shows a functional equivalent block diagram of theT1/T0synchroni-
zation and edge detectorlogic.The registers are clocked at the positive edge of the
internalsystem clock (
clk
I/O
).The latch is transparent in the highperiod of theinternal
system clock.
Theedge detector generates one clk
T1
/clk
T
0
pulse for each positive (CSn2:0 =7)or neg-
ative (CSn2:0 =6)edge it detects.
Figure 44. T1/T0 Pin Sampling
The synchronization and edge detectorlogic introduces a delay of 2.5 to 3.5 system
clock cyclesfrom an edge hasbeen applied to theT1/T0pin to the counter is updated.
Enabling anddisabling of the clock input must be done when T1/T0 hasbeen stable for
at least one system clock cycle, otherwiseitis a risk that a falseTimer/Counterclock
pulseis generated.
Each half period of theexternalclock applied must be longer than one system clock
cycletoensure correct sampling. Theexternalclock must beguaranteed to have less
than half the system clock frequency (f
ExtClk
<f
clk_I/O
/2) given a 50/50%duty cycle. Since
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clk
I/O