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212
ATmega8515(L)
2512A–AVR–04/02
BRIE k Branch ifInterrupt Enabled if(I=1) then PC ← PC+k+1 None
1/2
BRID k Branch ifInterrupt Disabled if(I=0) then PC ← PC+k+1 None
1/2
DATA TRANSFER INSTRUCTIONS
MOVRd, RrMove Between Registers Rd ← RrNone 1
MOVW Rd, RrCopy RegisterWord
Rd+1:Rd ← Rr+1:Rr
None 1
LDI Rd, K LoadImmediate Rd ← KNone 1
LD Rd, X LoadIndirectRd ← (X) None 2
LD Rd, X+ LoadIndirectand Post-Inc.Rd ← (X), X ← X+1 None 2
LD Rd, - X LoadIndirectand Pre-Dec. X ← X-1, Rd ← (X) None 2
LD Rd, Y LoadIndirectRd ← (Y) None 2
LD Rd, Y+ LoadIndirectand Post-Inc.Rd ← (Y), Y ← Y+1 None 2
LD Rd, - Y LoadIndirectand Pre-Dec. Y ← Y-1, Rd ← (Y) None 2
LDD Rd,Y+q LoadIndirect withDisplacement Rd ← (Y + q) None 2
LD Rd, Z LoadIndirectRd ← (Z) None 2
LD Rd, Z+ LoadIndirectand Post-Inc.Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z LoadIndirectand Pre-Dec. Z ← Z-1, Rd ← (Z) None 2
LDD Rd, Z+q LoadIndirect withDisplacement Rd ← (Z + q) None 2
LDS Rd, k LoadDirect from SRAM Rd ← (k) None 2
ST X, RrStore Indirect (X) ← RrNone 2
ST X+, RrStore Indirectand Post-Inc. (X) ← Rr, X ← X+1 None 2
ST -X,RrStore Indirectand Pre-Dec. X ← X-1,(X)← RrNone 2
ST Y, RrStore Indirect (Y) ← RrNone 2
ST Y+, RrStore Indirectand Post-Inc. (Y) ← Rr, Y ← Y+1 None 2
ST -Y,RrStore Indirectand Pre-Dec. Y ← Y-1,(Y)← RrNone 2
STDY+q,RrStore Indirect withDisplacement (Y + q) ← RrNone 2
ST Z, RrStore Indirect (Z) ← RrNone 2
ST Z+, RrStore Indirectand Post-Inc. (Z) ← Rr, Z ← Z+1 None 2
ST -Z, RrStore Indirectand Pre-Dec. Z ← Z-1,(Z)← RrNone 2
STDZ+q,RrStore Indirect withDisplacement (Z + q) ← RrNone 2
STSk,RrStore DirecttoSRAM(k)← RrNone 2
LPMLoad Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPMStoreProgram Memory (Z) ← R1:R0 None -
IN Rd, P InPortRd ← P None 1
OUTP, RrOut PortP← RrNone 1
PUSH Rr Push Register on Stack STACK ← RrNone 2
POPRd Pop Registerfrom Stack Rd ← STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O RegisterI/O(P,b) ← 1 None 2
CBI P,b ClearBit in I/O RegisterI/O(P,b) ← 0 None 2
LSL RdLogicalShift LeftRd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V1
LSRRdLogicalShiftRightRd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V1
ROL Rd Rotate LeftThroughCarry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V1
RORRd Rotate RightThroughCarry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V1
ASRRd ArithmeticShiftRightRd(n) ← Rd(n+1), n=0..6 Z,C,N,V1
SWAP RdSwapNibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None 1
BSET sFlag Set SREG(s) ← 1 SREG(s) 1
BCLR sFlag ClearSREG(s) ← 0 SREG(s) 1
BSTRr, b Bit Store from Register to T T ← Rr(b) T1
BLD Rd, b Bit loadfrom T to Register Rd(b) ← T None 1
SEC Set Carry C ← 1 C 1
CLC ClearCarry C ← 0 C 1
SEN Set Negative Flag N ← 1 N 1
CLN ClearNegative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1 Z 1
CLZ ClearZero Flag Z ← 0 Z 1
SEI GlobalInterrupt Enable I ← 1 I 1
CLI GlobalInterrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1 S 1
CLS ClearSigned Test Flag S ← 0 S 1
SEV Set TwosComplement Overflow.V← 1V1
CLV Clear TwosComplement Overflow V ← 0V1
SET Set T in SREG T ← 1T1
CLT Clear TinSREG T ← 0T1
SEH Set Half Carry Flag in SREG H ← 1 H 1
CLH ClearHalf Carry Flag in SREG H ← 0 H 1
MCU CONTROL INSTRUCTIONS