Owner manual

ATmega8515(L)

2512A–AVR–04/02

empty interrupt, otherwiseanew interrupt will occur oncetheinterrupt routine

terminates.

TheTransmit Complete (TXC) flag bit isset one when theentire frameinthetransmit

Shift Registerhasbeen shifted out and therearenonewdata currently present in the

transmit buffer.TheTXC flag bit is automatically clearedwhen a transmit complete inter-

ruptis executed, or it can be clearedbywriting a one to itsbit location. TheTXC flag is

useful in half-duplexcommunication interfaces(liketheRS-485 standard), wherea

transmitting application must enter Receive modeandfree the communication bus

immediately aftercompleting thetransmission.

When theTransmit Compete Interrupt Enable (TXCIE) bit in UCSRB isset, the USART

Transmit Complete Interrupt will beexecutedwhen theTXC flag becomesset (provided

that global interrupts areenabled). When thetransmit complete interruptis used, the

interrupt handling routine does not have to clear theTXC flag, this isdone automatically

when theinterruptis executed.

Parity Generator TheParityGeneratorcalculates the paritybit for the serialframe data. When paritybit is

enabled(UPM1 = 1), thetransmittercontrollogic inserts the paritybit between the last

data bit and the first stopbit of the frame that issent.

Disabling the Transmitter The disabling of theTransmitter(setting theTXEN to zero)will not become effective

until ongoing andpending transmissions are completed(i.e.,when theTransmit Shift

abled, theTransmitterwill no longer overridetheTxD pin.

Data Reception – The

USART Receiver

The USART Receiver is enabledbywriting theReceive Enable (RXEN) bit in the

UCSRB Register to one. When theReceiver is enabled, thenormalpin operation of the

RxD pin is overridden by the USART and given the function as the receiver’sserial

input. The baudrate, modeof operation andframe format must be set up once before

anyserialreception can be done. If synchronous operation is used, the clock on the

XCK pin will beused as transferclock.