Owner manual

136
ATmega8515(L)
2512A–AVR–04/02
Frame Formats A serialframe isdefined to be one character ofdata bitswithsynchronization bits(start
andstopbits), and optionally a paritybit for errorchecking. The USART accepts all 30
combinations of the following as validframe formats:
•1start bit
•5,6,7,8, or9data bits
•no, even or odd paritybit
•1or 2 stopbits
A frame startswith the start bit followedbythe least significant data bit. Then thenext
data bits, up toatotal of nine, are succeeding, ending with themost significant bit. If
enabled, the paritybit is inserted after the data bits, beforethe stopbits. When a com-
plete frame is transmitted, it can be directly followedbyanewframe, or the
communication line can be set to an idle (high) state. Figure 66 illustrates the possible
combinations of the frame formats. Bits inside brackets areoptional.
Figure 66. Frame Formats
St Start bit, always low
(n)Data bits(0to8)
PParitybit. Can beodd or even
Sp Stopbit, always high
IDLE Notransfers on the communication line (RxD or TxD).AnIDLE line must be
high.
The frame format usedbythe USART isset by the UCSZ2:0,UPM1:0andUSBSbits in
UCSRB andUCSRC.TheReceiver and Transmitter usethe same setting. Note that
changing the setting of any of these bitswill corruptall ongoing communication forboth
theReceiver and Transmitter.
The USART CharacterSiZe (UCSZ2:0)bitsselectthe number ofdata bits in the frame.
The USART Parity mode (UPM1:0)bits enableandset thetypeofparitybit. The selec-
tion between one or two stopbits isdone by the USART StopBit Select (USBS) bit. The
receiver ignores the secondstopbit. An FE (Frame Error) will thereforeonly be detected
in the caseswherethe first stopbit iszero.
Parity Bit Calculation The paritybit iscalculatedbydoing an exclusive-or of all the data bits. If odd parity is
used, the resultof theexclusive or is inverted.The relation between the paritybit and
data bits is asfollows::
P
even
Paritybit using even parity
P
odd
Paritybit using odd parity
d
n
Data bit n of the character
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME
P
even
d
n 1–
… d
3
d
2
d
1
d
0
0
P
odd
⊕⊕⊕⊕⊕⊕
d
n 1–
… d
3
d
2
d
1
d
0
1⊕⊕⊕⊕⊕⊕
=
=