Features • High-performance, Low-power AVR® 8-bit Microcontroller • RISC Architecture • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-programmable Flash Endurance: 1,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip
Pin Configurations Figure 1.
ATmega8515(L) Overview The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega8515(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.
ATmega8515(L) The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega8515(L) • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
ATmega8515(L) Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register file concept.
also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 162. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
ATmega8515(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
AVR ATmega8515 Memories This section describes the different memories in the ATmega8515. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8515 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega8515 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega8515(L) SRAM Data Memory Figure 9 shows how the ATmega8515 SRAM Memory is organized. The lower 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 512 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega8515. This SRAM will occupy an area in the remaining address locations in the 64K address space.
Figure 9. Data Memory Map Data Memory 32 Registers 64 I/O Registers $0000 - $001F $0020 - $005F $0060 Internal SRAM (512 x 8) $025F $0260 External SRAM (0 - 64K x 8) $FFFF Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10.
ATmega8515(L) EEPROM Data Memory The ATmega8515 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of SPI data downloading to the EEPROM, see page 189.
The EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 – – – – EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 EECR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8515 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt.
ATmega8515(L) • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega8515(L) The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
I/O Memory The I/O space definition of the ATmega8515 is shown in “Register Summary” on page 209. All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions.
ATmega8515(L) Figure 11. External Memory with Sector Select 0x0000 Internal Memory 0x25F 0x260 Lower Sector SRW01 SRW00 SRL[2..
data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal latch (typically “74x573” or equivalent) which is transparent when G is high. Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.
ATmega8515(L) time for the external memory in conjunction with the set-up requirement of the ATmega8515. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted low until data must be stable during a read sequence (tLLRL+ tRLRH - t DVRH in Table 99 to Table 106 on page 201). The different wait states are set up in software.
Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. DA7:0 Prev. Data Address DA7:0 (XMBK = 0) Prev. Data Address DA7:0 (XMBK = 1) Prev. Data XX Write Address Data WR Address Read Data Data RD Note: 1.
ATmega8515(L) Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. DA7:0 Prev. Data Address DA7:0 (XMBK = 0) Prev. Data Address DA7:0 (XMBK = 1) Prev. Data XX Write Address Data WR Address Read Data Data RD Note: 1.
SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits. Table 2. Sector Limits with Different Settings of SRL2..
ATmega8515(L) Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 – XMBK XMM2 XMM1 XMM0 PUD – PSR10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 6 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines.
Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only 60KB of External Memory is available by default (address space 0x0000 to 0x025F is reserved for Internal Memory). However, it is possible to take advantage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address.
ATmega8515(L) System Clock and Clock Options Clock Systems and their Distribution Figure 17 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 38. The clock systems are detailed below. Figure 17.
Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 5. Device Clocking Options Select(1) Device Clocking Option CKSEL3..
ATmega8515(L) Figure 18. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7. Table 7. Crystal Oscillator Operating Modes CKOPT CKSEL3..1 Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 1 101(2) 0.4 - 0.9 – 1 110 0.9 - 3.0 12 - 22 1 111 3.0 - 8.
Notes: Low-frequency Crystal Oscillator 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
ATmega8515(L) External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 19 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 19.
Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 12. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
ATmega8515(L) Table 14. Internal RC Oscillator Frequency Range. External Clock OSCCAL Value Min Frequency in Percentage of Nominal Frequency Max Frequency in Percentage of Nominal Frequency $00 50% 100% $7F 75% 150% $FF 100% 200% To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 20. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega8515(L) • Bits 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the three available sleep modes as shown in Table 16. Table 16. Sleep Mode Select Note: Idle Mode SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 Reserved 0 1 0 Power-down 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) 1 1 1 Reserved 1. Standby mode is only available with external crystals or resonators. When the SM2..
Standby Mode When the SM2..0 bits are written to 110, and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Table 17.
ATmega8515(L) Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega8515(L) Figure 21. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Control and Status Register (MCUCSR) Power-on Reset Circuit Brown-out Reset Circuit BODEN BODLEVEL Pull-up Resistor Spike Filter Reset Circuit Watchdog Timer Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 18. Reset Characteristics Symbol VPOT Parameter Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising)(1) 1.4 2.
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 18. The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATmega8515(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 18) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 24.
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 50 for details on operation of the Watchdog Timer. Figure 26. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
ATmega8515(L) Internal Voltage Reference ATmega8515 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 19. To save power, the reference is not always turned on. The reference is on during the following situations: 1.
Table 20. WDT Configuration as a Function of the Fuse Settings of S8515C and WDTON. Safety Level WDT Initial State How to Disable the WDT How to Change Timeout S8515C WDTON Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed sequence Unprogrammed Programmed 2 Enabled Always enabled Timed sequence Programmed Unprogrammed 0 Disabled Timed sequence No restriction Programmed Programmed 2 Enabled Always enabled Timed sequence Figure 27.
ATmega8515(L) 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 50. • Bits 2..
Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. Safety Level 0 This mode is compatible with the Watchdog operation found in AT90S4414/8515. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. The time-out period can be changed at any time without restriction.
ATmega8515(L) Interrupts Interrupt Vectors in ATmega8515 This section describes the specifics of the interrupt handling as performed in ATmega8515. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11. Table 22. Reset and Interrupt Vectors Vector No.
Table 23. Reset and Interrupt Vectors Placement(1) BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 $0000 $0001 1 1 $0000 Boot Reset Address + $0001 0 0 Boot Reset Address $0001 0 1 Boot Reset Address Boot Reset Address + $0001 Note: 1. The Boot Reset Address is shown in Table 78 on page 173. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
ATmega8515(L) When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code $000 RESET: ldi r16,high(RAMEND); Main program start Comments $001 out SPH,r16 $002 ldi r16,low(RAMEND) $003 out SPL,r16 $004 sei $005 ; Set stack pointer to top of RAM ; Enable interrupts xxx ; .
Moving Interrupts between Application and Boot Space General Interrupt Control Register – GICR The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 – – – IVSEL IVCE Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
ATmega8515(L) • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega8515(L) Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 29.
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step.
ATmega8515(L) signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 31. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 31.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega8515(L) Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 32 shows how the port pin control signals from the simplified Figure 29 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 32.
Table 25. Generic Description of Overriding Signals for Alternate Functions. Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega8515(L) Alternate Functions of Port A Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 26.
Table 28. Overriding Signals for Alternate Functions in PA3..
ATmega8515(L) DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit. • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5.
Table 30. Overriding Signals for Alternate Functions in PB7..
ATmega8515(L) Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 32. Table 32.
Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12 PUOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PUOV 0 0 0 0 DDOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) DDOV 1 1 1 1 PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PVOV A15 A14 A13 A12 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Table 34. Overriding Signals for Alternate Functions in PC3..
ATmega8515(L) Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 35. Table 35.
• RXD – Port D, Bit 0 RXD, Receive Data (Data input pin for USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit. Table 36 and Table 37 relate the alternate functions of Port D to the overriding signals shown in Figure 32 on page 61. Table 36. Overriding Signals for Alternate Functions PD7..
ATmega8515(L) Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 38. Table 38.
Register Description for I/O Ports Port A Data Register – PORTA Bit Port A Data Direction Register – DDRA Port A Input Pins Address – PINA 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2
ATmega8515(L) Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINC Port D Data Register – PORTD Bit Port D Data Direction Register – DDRD Port D Input Pins Address – PIND 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0
External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
ATmega8515(L) • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 41. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
ATmega8515(L) 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33.
inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 79. for details.
ATmega8515(L) clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0 Register access may seem complex, but this is not case.
ATmega8515(L) Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match. Also, the COM01:0 bits control the OC0 pin output source. Figure 36 shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega8515(L) the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
Figure 38. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin.
ATmega8515(L) Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 3) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the compare match between TCNT0 and OCR0 while upcounting, and set on the compare match while downcounting.
OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCn PCPW M = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega8515(L) Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 43.
as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used.
ATmega8515(L) Table 46. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 0 Normal port operation, OC0 disconnected. 0 1 Reserved 1 0 Clear OC0 on compare match, set OC0 at TOP. 1 1 Set OC0 on compare match, clear OC0 at TOP. Note: Description 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 83 for more details.
Timer/Counter Register – TCNT0 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock.
ATmega8515(L) Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OCF1B – ICF1 – TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega8515(L) the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 45.
16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATmega8515(L) Figure 46. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 160.) The input capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
ATmega8515(L) Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega8515(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 92. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
ATmega8515(L) how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 106. The Timer/Counter Overflow (TOV1) flag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register.
ATmega8515(L) measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the output compare flag generates an output compare interrupt.
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega8515(L) Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 50 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register Is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 50 on page 116. For fast PWM mode refer to Table 51 on page 116, and for phase correct and phase and frequency correct PWM refer to Table 52 on page 117.
ATmega8515(L) Clear Timer on Compare Match (CTC) Mode In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the output compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP.
ATmega8515(L) either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the TCNT1 and the OCR1x.
Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega8515(L) The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega8515(L) The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCF1x. Figure 55.
ATmega8515(L) Figure 57. Timer/Counter Timing Diagram, No Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 58 shows the same timing data, but with the prescaler enabled. Figure 58.
16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATmega8515(L) Table 52. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on compare match, OC1B reserved. 1 0 Clear OC1A/OC1B on compare match when up-counting. Set OC1A/OC1B on compare match when downcounting. 1 1 Set OC1A/OC1B on compare match when up-counting.
Table 53.
ATmega8515(L) When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the input capture function is disabled. • Bit 5: Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
Output Compare Register 1 A – OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] Output Compare Register 1 B – OCR1BH and OCR1BL OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the c
ATmega8515(L) • Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 51) is executed when the OCF1A flag, located in TIFR, is set.
• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.
ATmega8515(L) Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8515 and peripheral devices or between several AVR devices.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the 8 bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
ATmega8515(L) The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega8515(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
• Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 61 and Figure 62 for an example.
ATmega8515(L) SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 61 and Figure 62. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 56 and Table 57, as done below: Table 59.
ATmega8515(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
Figure 63. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. Refer to Figure 1 on page 2, Table 37 on page 70, and Table 31 on page 66 for USART pin placement.
ATmega8515(L) AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second buffer register has been added. The two buffer registers operate as a circular FIFO buffer.
Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
ATmega8515(L) Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication.
Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit.
ATmega8515(L) If used, the parity bit is located between the last data bit and first stop bit of a serial frame. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the Receiver depending on the usage.
be placed directly in the main routine, or be combined with initialization code for other I/O modules. Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega8515(L) Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16.
empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega8515(L) Receiving Frames with 5 to 8 Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is received (i.e.
Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR, and PE status flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.
ATmega8515(L) The receive function example reads all the I/O registers into the register file before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATmega8515(L) Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 67 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation.
Figure 69 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 69. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
ATmega8515(L) Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 62.
The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7).
ATmega8515(L) Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega8515(L) The transmit buffer can only be written when the UDRE flag in the UCSRA Register is set. Data written to UDR when the UDRE flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO.
• Bit 2 – PE: Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
ATmega8515(L) Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (character size) in a frame the receiver and transmitter use. • Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR.
Table 64. UPM Bits Settings UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 65.
ATmega8515(L) USART Baud Rate Registers – UBRRL and UBRRH Bit 15 14 13 12 URSEL – – – 11 10 9 8 UBRR[11:8] UBRRH UBRR[7:0] 7 Read/Write Initial Value 6 5 4 UBRRL 3 2 1 0 R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The UBRRH Register shares the same I/O location as the UCSRC Register. See the “Accessing UBRRH/UCSRC Registers” on page 149 section which describes how to access this register.
Table 68. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.
ATmega8515(L) Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.
Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
ATmega8515(L) Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz Baud Rate (bps) U2X = 0 fosc = 18.4320 MHz U2X = 1 U2X = 0 fosc = 20.0000 MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega8515(L) the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega8515(L) Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Figure 72.
ATmega8515(L) Table 74. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Store Program Memory Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCR • Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled.
ATmega8515(L) • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
Figure 73. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB 1 0 Z - REGISTER 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: Self-Programming the Flash 1. The different variables used in Figure 73 are listed in Table 80 on page 174. The program memory is updated in a page by page fashion.
ATmega8515(L) Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega8515(L) Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
; transfer data from RAM to Flash ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcrval, (1<
ATmega8515(L) ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret ATmega8515 Boot Loader Parameters In Table 78 through Table 80, the parameters used in the description of the Self-Programming are given. Table 78.
Table 80. Explanation of Different Variables used in Figure 73 and the Mapping to the Z-pointer(1) Corresponding Z-value Variable PCMSB 11 Most significant bit in the Program Counter. (The Program Counter is 12 bits PC[11:0]) PAGEMSB 4 Most significant bit which is used to address the words within one page (32 words in a page requires five bits PC [4:0]). ZPCMSB Z12 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega8515(L) Memory Programming Program and Data Memory Lock Bits The ATmega8515 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 82. The Lock bits can only be erased to “1” with the Chip Erase command. Table 81.
Table 82. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega8515(L) Table 84.
Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses are assumed to be at least 250 ns unless otherwise noted. Signal Names In this section, some pins of the ATmega8515 are referenced by signal names describing their functionality during parallel programming, see Figure 74 and Table 85.
ATmega8515(L) Table 86. Pin Values used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 87. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 88.
Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5 V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 86 on page 179 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode.
ATmega8515(L) Programming the Flash The Flash is organized in pages, see Table 89 on page 179. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
3. Wait until RDY/BSY goes high. (See Figure 76 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 75.
ATmega8515(L) Figure 76. Programming the Flash Waveforms F A DATA $10 B ADDR. LOW C D E DATA LOW DATA HIGH XX B ADDR. LOW C DATA LOW D DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 90 on page 179. When programming the EEPROM, the program data is latched into a page buffer.
Figure 77. Programming the EEPROM Waveforms K A DATA $10 G ADDR. HIGH B ADDR. LOW C E DATA XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 181 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte ($00 - $FF). 3. B: Load Address Low Byte ($00 - $FF). 4. Set OE to “0”, and BS1 to “0”.
ATmega8515(L) 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. Figure 78.
Figure 79. Mapping Between BS1, BS2, and the Fuse- and Lock Bits During Read Fuse Low Byte 0 DATA 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 181 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte ($00 - $02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”.
ATmega8515(L) Fi gure 8 1 . P a ra lle l P ro g r a mmin g Timin g , Lo a d in g S e qu e n c e w ith T im in g Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 80 (i.e. tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 82.
Table 91.
ATmega8515(L) Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Note: Serial Programming Pin Mapping In Table 92, the pin mapping for SPI programming is listed.
Serial Programming Algorithm When writing serial data to the ATmega8515, data is clocked on the rising edge of SCK. When reading data from the ATmega8515, data is clocked on the falling edge of SCK. See Figure 84, Figure 85, and Table 95 for timing details. To program and verify the ATmega8515 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 94.): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
ATmega8515(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
Table 94. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
ATmega8515(L) Serial Programming Characteristics Figure 85. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 95. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATmega8515L) 1/tCLCL tSHSL 0 Oscillator Period (ATmega8515, VCC = 4.5 5.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC +0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega8515(L) DC Characteristics (Continued) TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) Symbol Parameter Power Supply Current ICC Power-down mode(5) Condition Typ Max Units Active 4 MHz, VCC = 3V (ATmega8515L) 3 mA Active 8 MHz, VCC = 5V (ATmega8515) 11 mA Idle 4 MHz, VCC = 3V (ATmega8515L) 1.5 mA Idle 8 MHz, VCC = 5V (ATmega8515) 5.
External Clock Drive Waveforms Figure 86. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 96. External Clock Drive VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs Table 97.
ATmega8515(L) SPI Timing Characteristics See Figure 87 and Figure 88 for details. Table 98. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 58 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 88. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 198 MSB 17 ...
ATmega8515(L) External Data Memory Timing Table 99. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state 8 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 ns 2 tAVLL Address Valid A to ALE Low 57.5 0.
Table 101. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 375 3.0tCLCL ns 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns 325 3.0tCLCL-50 ns Table 102. External Data Memory Characteristics, 4.5 - 5.
ATmega8515(L) Table 103. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued) 4 MHz Oscillator 12 Symbol Parameter Min tRLRH RD Pulse Width 235 Max Variable Oscillator Min Max 1.0tCLCL-15 ns (1) 13 tDVWL Data Setup to WR Low 105 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 250 1.0tCLCL ns 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns Notes: 0.5tCLCL-20 Unit ns 1. This assumes 50% clock duty cycle.
Figure 89. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. Addr. Address 15 DA7:0 Prev. Data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Data 5 Read Address 11 10 8 12 RD Figure 90. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. Addr. Address 15 DA7:0 Prev.
ATmega8515(L) Figure 91. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. Addr. 15 DA7:0 Prev. Data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 92. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. Addr. 15 DA7:0 Prev.
ATmega8515 Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega8515(L) Figure 94. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 1 MHz at Vcc = 5V, T=25c) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.03 1.02 TA = -40˚C TA = -10˚C TA = 25˚C TA = 45˚C TA = 70˚C 1.01 1 0.99 FRc (MHz) TA = 85˚C 0.98 0.97 0.96 0.95 0.94 0.93 0.92 2.5 3 3.5 4 4.5 5 5.5 Vcc(V) Figure 95. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs.
Figure 96. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 2 MHz at Vcc = 5V, T=25c) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 2.1 2.05 TA = -10˚C TA = 25˚C TA = 45˚C TA = 70˚C TA = -40˚C FRc (MHz) 2 TA = 85˚C 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.5 Vcc(V) Figure 97. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 4 MHz at Vcc = 5V, T=25c) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.1 4.05 4 Vcc = 5.5V 3.
ATmega8515(L) Figure 98. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 4 MHz at Vcc = 5V, T=25c) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 4.1 TA = -40˚C 4.05 TA = -10˚C TA = 25˚C TA = 45˚C TA = 70˚C 4 3.95 TA = 85˚C FRc (MHz) 3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4 4.5 5 5.5 Vcc(V) Figure 99. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8 MHz at Vcc = 5V, T=25c) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
Figure 100. RC Oscillator Frequency vs. Operating Voltage (the devices are calibrated to 8 MHz at Vcc = 5V, T=25c) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.5 TA = -40˚C 8.3 TA = -10˚C TA = 25˚C TA = 45˚C TA = 70˚C 8.1 FRc (MHz) 7.9 TA = 85˚C 7.7 7.5 7.3 7.1 6.9 6.7 2.5 3 3.5 4 4.5 5 5.
ATmega8515(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $3F ($5F) SREG I T H S V N Z C Page 8 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 10 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 10 $3C ($5C) Reserved 54, 75 - $3B ($5B) GICR INT1 INT0 INT2 - - - IVSEL IVCE $3A ($5A) GIFR INTF1 INTF0 INTF2 - - - - - 76 $39 ($59) TIMSK TOIE1 OCIE1A OCIE1B - TICIE1 - TOIE0 OCIE0 90, 120 91, 121 $38
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
ATmega8515(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None LD Rd, - X Load Indirect and Pre-Dec.
ATmega8515(L) NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr.
Ordering Information(1) Speed (MHz) Power Supply 8 2.7 - 5.5V 16 Note: 4.5 - 5.
ATmega8515(L) Packaging Information 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 12.25(0.482) SQ 11.75(0.462) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC 10.10(0.394) SQ 9.90(0.386) 1.20(0.047) MAX 0.20(0.008) 0.09(0.004) 0˚~7˚ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) *Controlling dimension: millimetter REV.
40P6 40-lead, Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 52.71(2.075) 51.94(2.045) PIN 1 13.97(0.550) 13.46(0.530) 48.26(1.900) REF 4.83(0.190)MAX SEATING PLANE 0.38(0.015)MIN 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 1.65(0.065) 1.27(0.050) 0.56(0.022) 0.38(0.015) 15.88(0.625) 15.24(0.600) 0º ~ 15º REF 0.38(0.015) 0.20(0.008) 17.78(0.700)MAX *Controlling dimension: Inches REV.
ATmega8515(L) 44J 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Milimeters and (Inches)* JEDEC STANDARD MS-018 AC 1.14(0.045) X 45˚ 0.813(0.032) 0.660(0.026) PIN NO. 1 IDENTIFY 1.14(0.045) X 45˚ 16.70(0.656) SQ 16.50(0.650) 17.70(0.695) SQ 17.40(0.685) 1.27(0.050) TYP 12.70(0.500) REF SQ 0.318(0.0125) 0.191(0.0075) 16.00(0.630) SQ 15.00(0.590) 0.533(0.021) 0.330(0.013) 0.50(0.020)MIN 2.11(0.083) 1.57(0.062) 3.05(0.120) 2.29(0.090) 4.57(0.180) 4.19(0.165) 0.51(0.
44M1 D SEATING PLANE Marked pin#1 identifier E A1 TOP VIEW A3 A L SIDE VIEW PIN #1 CORNER D2 COMMON DIMENSIONS (*Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 0.25 REF A3 E2 b 0.18 D D2 2.25 e L 0.30 4.70 5.25 7.00 BSC 2.25 e b 0.23 7.00 BSC E E2 NOTE 4.70 5.25 0.50 BSC 0.35 0.55 0.75 BOTTOM VIEW NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1 07/23/01 R 218 DRAWING NO.
ATmega8515(L) Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Overview................................................................................................ 3 Block Diagram ...................................................................................................... Disclaimer ...................................
Internal Voltage Reference ................................................................................. 47 Watchdog Timer ................................................................................................. 47 Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 50 Interrupts ............................................................................................. 51 Interrupt Vectors in ATmega8515 ...............................................................
ATmega8515(L) Frame Formats ................................................................................................. USART Initialization.......................................................................................... Data Transmission – The USART Transmitter ................................................. Data Reception – The USART Receiver .......................................................... Asynchronous Data Reception ............................................................
44A ................................................................................................................... 40P6 ................................................................................................................. 44J .................................................................................................................... 44M1.................................................................................................................
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