Manual
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. Disclaimer
- 4. Resources
- 5. About Code Examples
- 6. Data Retention
- 7. AVR CPU Core
- 8. Memories
- 9. System Clock and their Distribution
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. Interrupts
- 13. External Interrupts
- 13.1 Pin Change Interrupt Timing
- 13.2 Register Description
- 13.2.1 EICRA – External Interrupt Control Register A
- 13.2.2 EIMSK – External Interrupt Mask Register
- 13.2.3 EIFR – External Interrupt Flag Register
- 13.2.4 PCICR – Pin Change Interrupt Control Register
- 13.2.5 PCIFR – Pin Change Interrupt Flag Register
- 13.2.6 PCMSK3 – Pin Change Mask Register 3
- 13.2.7 PCMSK2 – Pin Change Mask Register 2
- 13.2.8 PCMSK1 – Pin Change Mask Register 1
- 13.2.9 PCMSK0 – Pin Change Mask Register 0
- 14. I/O-Ports
- 14.1 Overview
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
- 14.4.1 MCUCR – MCU Control Register
- 14.4.2 PORTB – Port B Data Register
- 14.4.3 DDRB – Port B Data Direction Register
- 14.4.4 PINB – Port B Input Pins Address
- 14.4.5 PORTC – Port C Data Register
- 14.4.6 DDRC – Port C Data Direction Register
- 14.4.7 PINC – Port C Input Pins Address
- 14.4.8 PORTD – Port D Data Register
- 14.4.9 DDRD – Port D Data Direction Register
- 14.4.10 PIND – Port D Input Pins Address
- 14.4.11 PORTE – Port E Data Register
- 14.4.12 DDRE – Port E Data Direction Register
- 14.4.13 PINE – Port E Input Pins Address
- 15. 8-bit Timer/Counter0 with PWM
- 15.1 Features
- 15.2 Overview
- 15.3 Timer/Counter Clock Sources
- 15.4 Counter Unit
- 15.5 Output Compare Unit
- 15.6 Compare Match Output Unit
- 15.7 Modes of Operation
- 15.8 Timer/Counter Timing Diagrams
- 15.9 Register Description
- 15.9.1 TCCR0A – Timer/Counter Control Register A
- 15.9.2 TCCR0B – Timer/Counter Control Register B
- 15.9.3 TCNT0 – Timer/Counter Register
- 15.9.4 OCR0A – Output Compare Register A
- 15.9.5 OCR0B – Output Compare Register B
- 15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
- 15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
- 16. 16-bit Timer/Counter1 with PWM
- 16.1 Features
- 16.2 Overview
- 16.3 Accessing 16-bit Registers
- 16.4 Timer/Counter Clock Sources
- 16.5 Counter Unit
- 16.6 Input Capture Unit
- 16.7 Output Compare Units
- 16.8 Compare Match Output Unit
- 16.9 Modes of Operation
- 16.10 Timer/Counter Timing Diagrams
- 16.11 Register Description
- 16.11.1 TCCR1A – Timer/Counter1 Control Register A
- 16.11.2 TCCR1B – Timer/Counter1 Control Register B
- 16.11.3 TCCR1C – Timer/Counter1 Control Register C
- 16.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 16.11.7 ICR1H and ICR1L – Input Capture Register 1
- 16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
- 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
- 17. Timer/Counter0 and Timer/Counter1 Prescalers
- 18. PSC – Power Stage Controller
- 18.1 Features
- 18.2 Overview
- 18.3 Accessing 16-bit Registers
- 18.4 PSC Description
- 18.5 Functional Description
- 18.6 Update of Values
- 18.7 Overlap Protection
- 18.8 Signal Description
- 18.9 PSC Input
- 18.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.
- 18.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
- 18.12 Analog Synchronization
- 18.13 Interrupt Handling
- 18.14 PSC Clock Sources
- 18.15 Interrupts
- 18.16 Register Description
- 18.16.1 POC – PSC Output Configuration
- 18.16.2 PSYNC – PSC Synchro Configuration
- 18.16.3 POCRnSAH and POCRnSAL – PSC Output Compare SA Register
- 18.16.4 POCRnRAH and POCRnRAL – PSC Output Compare RA Register
- 18.16.5 POCRnSBH and POCRnSBL – PSCOutput Compare SB Register
- 18.16.6 POCRnRBH and POCRnRBL – PSC Output Compare RB Register
- 18.16.7 PCNF – PSC Configuration Register
- 18.16.8 PCTL – PSC Control Register
- 18.16.9 PMICn – PSC Module n Input Control Register
- 18.16.10 PSC Interrupt Mask Register – PIM
- 18.16.11 PIFR – PSC Interrupt Flag Register
- 19. SPI – Serial Peripheral Interface
- 20. CAN – Controller Area Network
- 20.1 Features
- 20.2 Overview
- 20.3 CAN Protocol
- 20.3.1 Principles
- 20.3.2 Message Formats
- 20.3.3 CAN Bit Timing
- 20.3.3.1 Bit Construction
- 20.3.3.2 Synchronization Segment
- 20.3.3.3 Propagation Time Segment
- 20.3.3.4 Phase Segment 1
- 20.3.3.5 Sample Point
- 20.3.3.6 Phase Segment 2
- 20.3.3.7 Information Processing Time
- 20.3.3.8 Bit Lengthening
- 20.3.3.9 Bit Shortening
- 20.3.3.10 Synchronization Jump Width
- 20.3.3.11 Programming the Sample Point
- 20.3.3.12 Synchronization
- 20.3.4 Arbitration
- 20.3.5 Errors
- 20.4 CAN Controller
- 20.5 CAN Channel
- 20.6 Message Objects
- 20.7 CAN Timer
- 20.8 Error Management
- 20.9 Interrupts
- 20.10 Register Description
- 20.10.1 CANGCON – CAN General Control Register
- 20.10.2 CANGSTA – CAN General Status Register
- 20.10.3 CANGIT – CAN General Interrupt Register
- 20.10.4 CANGIE – CAN General Interrupt Enable Register
- 20.10.5 CANEN2 and CANEN1 – CAN Enable MOb Registers
- 20.10.6 CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers
- 20.10.7 CANSIT2 and CANSIT1 – CAN Status Interrupt MOb Registers
- 20.10.8 CANBT1 – CAN Bit Timing Register 1
- 20.10.9 CANBT2 – CAN Bit Timing Register 2
- 20.10.10 CANBT3 – CAN Bit Timing Register 3
- 20.10.11 CANTCON – CAN Timer Control Register
- 20.10.12 CANTIML and CANTIMH – CAN Timer Registers
- 20.10.13 CANTTCL and CANTTCH – CAN TTC Timer Registers
- 20.10.14 CANTEC – CAN Transmit Error Counter Register
- 20.10.15 CANREC – CAN Receive Error Counter Register
- 20.10.16 CANHPMOB – CAN Highest Priority MOb Register
- 20.10.17 CANPAGE – CAN Page MOb Register
- 20.11 MOb Registers
- 20.11.1 CANSTMOB – CAN MOb Status Register
- 20.11.2 CANCDMOB – CAN MOb Control and DLC Register
- 20.11.3 CANIDT1, CANIDT2, CANIDT3, and CANIDT4 – CAN Identifier Tag Registers
- 20.11.4 CANIDM1, CANIDM2, CANIDM3, and CANIDM4 – CAN Identifier Mask Registers
- 20.11.5 CANSTML and CANSTMH – CAN Time Stamp Registers
- 20.11.6 CANMSG – CAN Data Message Register
- 20.12 Examples of CAN Baud Rate Setting
- 21. LIN / UART - Local Interconnect Network Controller or UART
- 21.1 Features
- 21.2 Overview
- 21.3 LIN Protocol
- 21.4 LIN / UART Controller
- 21.5 LIN / UART Description
- 21.5.1 Reset
- 21.5.2 Clock
- 21.5.3 LIN Protocol Selection
- 21.5.4 Configuration
- 21.5.5 Busy Signal
- 21.5.6 Bit Timing
- 21.5.7 Data Length
- 21.5.8 xxOK Flags
- 21.5.9 xxERR Flags
- 21.5.10 Frame Time Out
- 21.5.11 Break-in-data
- 21.5.12 Checksum
- 21.5.13 Interrupts
- 21.5.14 Message Filtering
- 21.5.15 Data Management
- 21.5.16 OCD Support
- 21.6 Register Description
- 21.6.1 LINCR – LIN Control Register
- 21.6.2 LINSIR – LIN Status and Interrupt Register
- 21.6.3 LINENIR – LIN Enable Interrupt Register
- 21.6.4 LINERR – LIN Error Register
- 21.6.5 LINBTR – LIN Bit Timing Register
- 21.6.6 LINBRR – LIN Baud Rate Register
- 21.6.7 LINDLR – LIN Data Length Register
- 21.6.8 LINIDR – LIN Identifier Register
- 21.6.9 LINSEL – LIN Data Buffer Selection Register
- 21.6.10 LINDAT – LIN Data Register
- 22. ADC – Analog to Digital Converter
- 22.1 Features
- 22.2 Operation
- 22.3 Starting a Conversion
- 22.4 Prescaling and Conversion Timing
- 22.5 Changing Channel or Reference Selection
- 22.6 ADC Noise Canceler
- 22.7 ADC Conversion Result
- 22.8 Temperature Measurement
- 22.9 Amplifier
- 22.10 Register Description
- 22.10.1 ADMUX – ADC Multiplexer Register
- 22.10.2 Bit 4: 0 – MUX[4:0]: ADC Channel Selection Bits
- 22.10.3 ADCSRA – ADC Control and Status Register A
- 22.10.4 ADCSRB – ADC Control and Status Register B
- 22.10.5 ADCH and ADCL – ADC Result Data Registers
- 22.10.6 DIDR0 – Digital Input Disable Register 0
- 22.10.7 DIDR1 – Digital Input Disable Register 1
- 22.10.8 AMP0CSR – Amplifier 0 Control and Status register
- 22.10.9 AMP1CSR – Amplifier 1 Control and Status register
- 22.10.10 AMP2CSR – Amplifier 2 Control and Status register
- 23. ISRC - Current Source
- 24. AC – Analog Comparator
- 24.1 Features
- 24.2 Overview
- 24.3 Use of ADC Amplifiers
- 24.4 Register Description
- 24.4.1 AC0CON – Analog Comparator 0 Control Register
- 24.4.2 AC1CON – Analog Comparator 1Control Register
- 24.4.3 AC2CON – Analog Comparator 2 Control Register
- 24.4.4 AC3CON – Analog Comparator 3 Control Register
- 24.4.5 ACSR – Analog Comparator Status Register
- 24.4.6 DIDR0 – Digital Input Disable Register 0
- 24.4.7 DIDR1 – Digital Input Disable Register 1
- 25. DAC – Digital to Analog Converter
- 26. debugWIRE On-chip Debug System
- 27. Boot Loader Support – Read-While-Write Self-Programming
- 27.1 Overview
- 27.2 Application and Boot Loader Flash Sections
- 27.3 Read-While-Write and No Read-While-Write Flash Sections
- 27.4 Boot Loader Lock Bits
- 27.5 Entering the Boot Loader Program
- 27.6 Addressing the Flash During Self-Programming
- 27.7 Self-Programming the Flash
- 27.7.1 Performing Page Erase by SPM
- 27.7.2 Filling the Temporary Buffer (Page Loading)
- 27.7.3 Performing a Page Write
- 27.7.4 Using the SPM Interrupt
- 27.7.5 Consideration While Updating BLS
- 27.7.6 Prevent Reading the RWW Section During Self-Programming
- 27.7.7 Setting the Boot Loader Lock Bits by SPM
- 27.7.8 EEPROM Write Prevents Writing to SPMCSR
- 27.7.9 Reading the Fuse and Lock Bits from Software
- 27.7.10 Reading the Signature Row from Software
- 27.7.11 Preventing Flash Corruption
- 27.7.12 Programming Time for Flash when Using SPM
- 27.7.13 Simple Assembly Code Example for a Boot Loader
- 27.7.14 ATmega16M1 - 16K - Flash Boot Loader Parameters
- 27.7.15 ATmega32M1 - 32K - Flash Boot Loader Parameters
- 27.7.16 ATmega64M1 - 64K - Flash Boot Loader Parameters
- 27.8 Register Description
- 28. Memory Programming
- 28.1 Program And Data Memory Lock Bits
- 28.2 Fuse Bits
- 28.3 PSC Output Behavior During Reset
- 28.4 Signature Bytes
- 28.5 Calibration Byte
- 28.6 Page Size
- 28.7 Parallel Programming Parameters, Pin Mapping, and Commands
- 28.8 Serial Programming Pin Mapping
- 28.9 Parallel Programming
- 28.9.1 Enter Programming Mode
- 28.9.2 Considerations for Efficient Programming
- 28.9.3 Chip Erase
- 28.9.4 Programming the Flash
- 28.9.5 Programming the EEPROM
- 28.9.6 Reading the Flash
- 28.9.7 Reading the EEPROM
- 28.9.8 Programming the Fuse Low Bits
- 28.9.9 Programming the Fuse High Bits
- 28.9.10 Programming the Extended Fuse Bits
- 28.9.11 Programming the Lock Bits
- 28.9.12 Reading the Fuse and Lock Bits
- 28.9.13 Reading the Signature Bytes
- 28.9.14 Reading the Calibration Byte
- 28.9.15 Parallel Programming Characteristics
- 28.10 Serial Downloading
- 29. Electrical Characteristics
- 30. Typical Characteristics – TBD
- 31. Register Summary
- 32. Instruction Set Summary
- 33. Errata
- 34. Ordering Information
- 35. Packaging Information
- 36. Datasheet Revision History
- Table of Contents
323
8209A–AVR–08/09
ATmega16M1/32M1/64M1
(0xBE) Reserved – – – – – – – –
(0xBD) Reserved – – – – – – – –
(0xBC)
(5)
PIFR – – – – PEV2 PEV1 PEV0 PEOP page 153
(0xBB)
(5)
PIM – – – – PEVE2 PEVE1 PEVE0 PEOPE page 152
(0xBA)
(5)
PMIC2 POVEN2 PISEL2 PELEV2 PFLTE2 PAOC2 PRFM22 PRFM21 PRFM20 page 151
(0xB9)
(5)
PMIC1 POVEN1 PISEL1 PELEV1 PFLTE1 PAOC1 PRFM12 PRFM11 PRFM10 page 151
(0xB8)
(5)
PMIC0 POVEN0 PISEL0 PELEV0 PFLTE0 PAOC0 PRFM02 PRFM01 PRFM00 page 151
(0xB7)
(5)
PCTL PPRE1 PPRE0 PCLKSEL – – – PCCYC PRUN page 151
(0xB6)
(5)
POC – – POEN2B POEN2A POEN1B POEN1A POEN0B POEN0A page 147
(0xB5)
(5)
PCNF – – PULOCK PMODE POPB POPA – – page 150
(0xB4)
(5)
PSYNC – – PSYNC21 PSYNC20 PSYNC11 PSYNC10 PSYNC01 PSYNC00 page 148
(0xB3)
(5)
POCR_RBH – – – – POCR_RB11 POCR_RB10 POCR_RB9 POCR_RB8 page 150
(0xB2)
(5)
POCR_RBL POCR_RB7 POCR_RB6 POCR_RB5 POCR_RB4 POCR_RB3 POCR_RB2 POCR_RB1 POCR_RB0 page 150
(0xB1)
(5)
POCR2SBH – – – – POCR2SB11 POCR2SB10 POCR2SB9 POCR2SB8 page 149
(0xB0)
(5)
POCR2SBL POCR2SB7 POCR2SB6 POCR2SB5 POCR2SB4 POCR2SB3 POCR2SB2 POCR2SB1 POCR2SB0 page 149
(0xAF)
(5)
POCR2RAH – – – – POCR2RA11 POCR2RA10 POCR2RA9 POCR2RA8 page 149
(0xAE)
(5)
POCR2RAL POCR2RA7 POCR2RA6 POCR2RA5 POCR2RA4 POCR2RA3 POCR2RA2 POCR2RA1 POCR2RA0 page 149
(0xAD)
(5)
POCR2SAH – – – – POCR2SA11 POCR2SA10 POCR2SA9 POCR2SA8 page 149
(0xAC)
(5)
POCR2SAL POCR2SA7 POCR2SA6 POCR2SA5 POCR2SA4 POCR2SA3 POCR2SA2 POCR2SA1 POCR2SA0 page 149
(0xAB)
(5)
POCR1SBH – – – – POCR1SB11 POCR1SB10 POCR1SB9 POCR1SB8 page 149
(0xAA)
(5)
POCR1SBL POCR1SB7 POCR1SB6 POCR1SB5 POCR1SB4 POCR1SB3 POCR1SB2 POCR1SB1 POCR1SB0 page 149
(0xA9)
(5)
POCR1RAH – – – – POCR1RA11 POCR1RA10 POCR1RA9 POCR1RA8 page 149
(0xA8)
(5)
POCR1RAL POCR1RA7 POCR1RA6 POCR1RA5 POCR1RA4 POCR1RA3 POCR1RA2 POCR1RA1 POCR1RA0 page 149
(0xA7)
(5)
POCR1SAH – – – – POCR1SA11 POCR1SA10 POCR1SA9 POCR1SA8 page 149
(0xA6)
(5)
POCR1SAL POCR1SA7 POCR1SA6 POCR1SA5 POCR1SA4 POCR1SA3 POCR1SA2 POCR1SA1 POCR1SA0 page 149
(0xA5)
(5)
POCR0SBH – – – – POCR0SB11 POCR0SB10 POCR0SB9 POCR0SB8 page 149
(0xA4)
(5)
POCR0SBL POCR0SB7 POCR0SB6 POCR0SB5 POCR0SB4 POCR0SB3 POCR0SB2 POCR0SB1 POCR0SB0 page 149
(0xA3)
(5)
POCR0RAH – – – – POCR0RA11 POCR0RA10 POCR0RA9 POCR0RA8 page 149
(0xA2)
(5)
POCR0RAL POCR0RA7 POCR0RA6 POCR0RA5 POCR0RA4 POCR0RA3 POCR0RA2 POCR0RA1 POCR0RA0 page 149
(0xA1)
(5)
POCR0SAH – – – – POCR0SA11 POCR0SA10 POCR0SA9 POCR0SA8 page 149
(0xA0)
(5)
POCR0SAL POCR0SA7 POCR0SA6 POCR0SA5 POCR0SA4 POCR0SA3 POCR0SA2 POCR0SA1 POCR0SA0 page 149
(0x9F) Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) AC3CON AC3EN AC3IE AC3IS1 AC3IS0 – AC3M2 AC3M1 AC3M0 page 260
(0x96) AC2CON AC2EN AC2IE AC2IS1 AC2IS0 – AC2M2 AC2M1 AC2M0 page 260
(0x95) AC1CON AC1EN AC1IE AC1IS1 AC1IS0 AC1ICE AC1M2 AC1M1 AC1M0 page 259
(0x94) AC0CON AC0EN AC0IE AC0IS1 AC0IS0 ACCKSEL AC0M2 AC0M1 AC0M0 page 258
(0x93) Reserved – – – – – – – –
(0x92) DACH - / DAC9 - / DAC8 - / DAC7 - / DAC6 - / DAC5 - / DAC4 DAC9 / DAC3 DAC8 / DAC2 page 268
(0x91) DACL DAC7 / DAC1 DAC6 /DAC0 DAC5 / - DAC4 / - DAC3 / - DAC2 / - DAC1 / - DAC0 / page 268
(0x90) DACON DAATE DATS2 DATS1 DATS0
– DALA DAOE DAEN page 267
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) OCR1BH OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11 OCR1B10 OCR1B9 OCR1B8 page 128
(0x8A) OCR1BL OCR1B7 OCR1B6 OCR1B5 OCR1B4 OCR1B3 OCR1B2 OCR1B1 OCR1B0 page 128
(0x89) OCR1AH OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11 OCR1A10 OCR1A9 OCR1A8 page 128
(0x88) OCR1AL OCR1A7 OCR1A6 OCR1A5 OCR1A4 OCR1A3 OCR1A2 OCR1A1 OCR1A0 page 128
(0x87) ICR1H ICR115 ICR114 ICR113 ICR112 ICR111 ICR110 ICR19 ICR18 page 129
(0x86) ICR1L ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 page 129
(0x85) TCNT1H TCNT115 TCNT114 TCNT113 TCNT112 TCNT111 TCNT110 TCNT19 TCNT18 page 128
(0x84) TCNT1L TCNT17 TCNT16 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 page 128
(0x83) Reserved – – – – – – – –
(0x82) TCCR1C FOC1A FOC1B – – – – – – page 127
(0x81) TCCR1B ICNC1 ICES1
– WGM13 WGM12 CS12 CS11 CS10 page 126
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0
– –WGM11WGM10 page 124
(0x7F) DIDR1 – AMP2PD ACMP0D AMP0PD AMP0ND ADC10D ADC9D ADC8D page 248
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D page 248
(0x7D) Reserved – – – – – – – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page