Manual

246
8209A–AVR–08/09
ATmega16M1/32M1/64M1
• Bit 6 – ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free
running mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register.
See Table 22-7 on page 247.
• Bit 4 – ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the
conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3 – ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2:0 – ADPS[2:0]: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of
the ADC.
The different setting are shown in Table 22-6.
22.10.4 ADCSRB – ADC Control and Status Register B
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with
an ADC clock frequency higher than 200KHz.
Table 22-6. ADC Prescaler Selection
ADPS[2:0] Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Bit 76543210
ADHSM ISRCEN AREFEN - ADTS3 ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0