Features • High Performance, Low Power AVR ® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • • • – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory – 16/32/64K Bytes Flash of In-System Programmable Program Memory – 512B/1K/2K Bytes of In-System Programmable EEPROM – 1/2/4K Bytes Internal SRAM – Write/Eras
ATmega16M1/32M1/64M1 1. Pin Configurations PB7 (ADC4/PSCOUT0B/SCK/PCINT7) PB6 (ADC7/PSCOUT1B/PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) PD0 (PCINT16/PSCOUT0A) PC0(PCINT8/INT3/PSCOUT1A) 32 31 30 29 28 27 26 25 PE0 (PCINT24/RESET/OCD) ATmega16M1/32M1/64M1 TQFP32/QFN32 (7*7 mm) Package. PD1(PCINT17/PSCIN0/CLKO) Figure 1-1.
ATmega16M1/32M1/64M1 1.1 Pin Descriptions Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type 5 GND Power Ground: 0V reference 20 AGND Power Analog Ground: 0V reference for analog part 4 VCC Power Power Supply 19 AVCC Power Analog Power Supply: This is the power supply voltage for analog part Name, Function & Alternate Function For a normal use this pin must be connected. 21 AREF Power Analog Reference : reference for analog converter .
ATmega16M1/32M1/64M1 Table 1-1.
ATmega16M1/32M1/64M1 Table 1-1.
ATmega16M1/32M1/64M1 2.1 Block Diagram Figure 2-1.
ATmega16M1/32M1/64M1 The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
ATmega16M1/32M1/64M1 2.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega16M1/32M1/64M1 3. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 5.
ATmega16M1/32M1/64M1 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
ATmega16M1/32M1/64M1 ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
ATmega16M1/32M1/64M1 specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.
ATmega16M1/32M1/64M1 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega16M1/32M1/64M1 Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.
ATmega16M1/32M1/64M1 7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit Read/Write Initial Value 7.
ATmega16M1/32M1/64M1 7.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
ATmega16M1/32M1/64M1 Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
ATmega16M1/32M1/64M1 8. Memories 8.1 Overview This section describes the different memories in the ATmega16M1/32M1/64M1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16M1/32M1/64M1 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
ATmega16M1/32M1/64M1 8.3 SRAM Data Memory Figure 8-2 shows how the ATmega16M1/32M1/64M1 SRAM Memory is organized. The ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega16M1/32M1/64M1 Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
ATmega16M1/32M1/64M1 8.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
ATmega16M1/32M1/64M1 8.7 8.7.1 Register Description EEARH and EEARL – The EEPROM Address Registers Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – - EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15:10 – Res: Reserved These bits are reserved and will always read as zero.
ATmega16M1/32M1/64M1 EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 8-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.
ATmega16M1/32M1/64M1 When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM.
ATmega16M1/32M1/64M1 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega16M1/32M1/64M1 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega16M1/32M1/64M1 9. System Clock and their Distribution 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 38. The clock systems are detailed below. Figure 9-1.
ATmega16M1/32M1/64M1 9.1.4 PLL Clock – clkPLL The PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 9.
ATmega16M1/32M1/64M1 Table 9-2. 9.3 Number of Watchdog Oscillator Cycles Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536) Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8.
ATmega16M1/32M1/64M1 Table 9-3. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(2) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22 Notes: 1. The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..
ATmega16M1/32M1/64M1 9.5 Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 34 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-1. If selected, it will operate with no external components.
ATmega16M1/32M1/64M1 9.6 9.6.1 PLL Internal PLL The internal PLL in ATmega16M1/32M1/64M1 generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the Figure 9-3 on page 33. The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time.
ATmega16M1/32M1/64M1 Figure 9-3. PCK Clocking System OSCCAL PLLF PLLE PLOCK Lock Detector RC OSCILLATOR 8 MHz DIVIDE BY 8 PLL 64x CLK PLL DIVIDE BY 2 DIVIDE BY 4 CK SOURCE XTAL1 XTAL2 9.7 OSCILLATORS 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator. 9.
ATmega16M1/32M1/64M1 When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-9. Table 9-9. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.
ATmega16M1/32M1/64M1 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 9.11 9.11.
ATmega16M1/32M1/64M1 When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLKPLL for Fast Peripherals. After the PLL is enabled, it takes about 100 ms for the PLL to lock. 9.11.
ATmega16M1/32M1/64M1 Table 9-10.
ATmega16M1/32M1/64M1 10. Power Management and Sleep Modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 10.2 Sleep Modes Figure 9-1 on page 27 presents the different clock systems in the ATmega16M1/32M1/64M1, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega16M1/32M1/64M1 setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 10.
ATmega16M1/32M1/64M1 Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. 10.8 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating.
ATmega16M1/32M1/64M1 the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “I/O-Ports” on page 65 for details on which pins are enabled.
ATmega16M1/32M1/64M1 • Bit 1 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 10.9.
ATmega16M1/32M1/64M1 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega16M1/32M1/64M1 Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 313.
ATmega16M1/32M1/64M1 Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 313) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega16M1/32M1/64M1 Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 47 for details on operation of the Watchdog Timer. Figure 11-6. Watchdog Reset During Operation CC CK 11.
ATmega16M1/32M1/64M1 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. 4. When the DAC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC or the DAC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC or DAC is used.
ATmega16M1/32M1/64M1 expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
ATmega16M1/32M1/64M1 Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
ATmega16M1/32M1/64M1 Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR r16, (1<
ATmega16M1/32M1/64M1 11.5 11.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
ATmega16M1/32M1/64M1 and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.
ATmega16M1/32M1/64M1 . Table 11-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATmega16M1/32M1/64M1 12. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega16M1/32M1/64M1. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 16. 12.1 Interrupt Vectors in ATmega16M1/32M1/64M1 Table 12-1. Reset and Interrupt Vectors Vector No.
ATmega16M1/32M1/64M1 Table 12-1. Reset and Interrupt Vectors Vector No. Program Address 29 Source Interrupt Definition 0x0038 WDT Watchdog Time-Out Interrupt 30 0x003A EE READY EEPROM Ready 31 0x003C SPM READY Store Program Memory Ready Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 272. 2.
ATmega16M1/32M1/64M1 0x01C jmp TIM1_OVF ; Timer1 Overflow Handler 0x01E jmp TIM0_COMPA ; Timer0 Compare A Handler 0x020 jmp TIM0_COMPB ; Timer0 Compare B Handler 0x022 jmp TIM0_OVF ; Timer0 Overflow Handler 0x024 jmp CAN_INT ; CAN MOB,Burst,General Errors Handler 0x026 jmp CAN_TOVF ; CAN Timer Overflow Handler 0x028 jmp LIN_TC ; LIN Transfer Complete Handler 0x02A jmp LIN_ERR ; LIN Error Handler 0x02C jmp PCINT0 ; Pin Change Int Request 0 Handler 0x02E jmp PCINT1 ; Pin
ATmega16M1/32M1/64M1 Address Labels Code Comments .org 0x002 0x002 jmp ANA_COMP_0 ; Analog Comparator 0 Handler 0x004 jmp ANA_COMP_1 ; Analog Comparator 1 Handler ... ... ... ; 0x03C jmp SPM_RDY ; Store Program Memory Ready Handler ; .
ATmega16M1/32M1/64M1 12.2 12.2.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 SPIPS – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
ATmega16M1/32M1/64M1 Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
ATmega16M1/32M1/64M1 13. External Interrupts The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14:8 pin toggles.
ATmega16M1/32M1/64M1 13.2 13.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
ATmega16M1/32M1/64M1 13.2.3 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 – – – – INTF3 INTF2 INTF1 INTF0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIFR • Bit 7:4 – Res: Reserved These bits are reserved and will always read as zero. • Bit 3:0 – INTF[3:0]: External Interrupt Flag 3:0 When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes set (one).
ATmega16M1/32M1/64M1 13.2.5 PCIFR – Pin Change Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 – – – – PCIF3 PCIF2 PCIF1 PCIF0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCIFR • Bit 7:4 - Res: Reserved These bits are reserved and will always read as zero. • Bit 3 - PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT26:24 pin triggers an interrupt request, PCIF3 becomes set (one).
ATmega16M1/32M1/64M1 13.2.7 PCMSK2 – Pin Change Mask Register 2 Bit 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK2 • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16 Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATmega16M1/32M1/64M1 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega16M1/32M1/64M1 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET 1 Q Pxn D 0 PORTxn Q CLR WPx DATA BUS RDx RESET WRx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK Note: 14.2.
ATmega16M1/32M1/64M1 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 14.2.
ATmega16M1/32M1/64M1 Figure 14-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega16M1/32M1/64M1 values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16, (1<
ATmega16M1/32M1/64M1 14.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5 shows how the port pin control signals from the simplified Figure 14-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 14-5.
ATmega16M1/32M1/64M1 Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega16M1/32M1/64M1 14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Table 14-3.
ATmega16M1/32M1/64M1 PCINT6, Pin Change Interrupt 6. • ADC6/INT2/ACMPN1/AMP2-/PCINT5 – Bit 5 ADC6, Analog to Digital Converter, input channel 6. INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU. ACMPN1, Analog Comparator 1 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT5, Pin Change Interrupt 5.
ATmega16M1/32M1/64M1 Table 14-4 and Table 14-5 relates the alternate functions of Port B to the overriding signals shown in Figure 14-5 on page 70. Table 14-4. Overriding Signals for Alternate Functions in PB7..
ATmega16M1/32M1/64M1 14.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-6. Table 14-6.
ATmega16M1/32M1/64M1 • ADC10/ACMP1/PCINT14 – Bit 6 ADC10, Analog to Digital Converter, input channel 10. ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT14, Pin Change Interrupt 14. • ADC9/ACMP3/AMP1+/PCINT13 – Bit 5 ADC9, Analog to Digital Converter, input channel 9. ACMP3, Analog Comparator 3 Positive Input.
ATmega16M1/32M1/64M1 SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit. PCINT9, Pin Change Interrupt 9. • PCINT8/PSCOUT1A/INT3 – Bit 0 PSCOUT1A, Output 1A of PSC.
ATmega16M1/32M1/64M1 Table 14-8. Overriding Signals for Alternate Functions in PC3..
ATmega16M1/32M1/64M1 14.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-9. Table 14-9.
ATmega16M1/32M1/64M1 ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU. PCINT22, Pin Change Interrupt 23. • ADC2/ACMP2/PCINT21 – Bit 5 ADC2, Analog to Digital Converter, input channel 2. ACMP2, Analog Comparator 1 Positive Input.
ATmega16M1/32M1/64M1 OC1A, Output Compare Match A output: This pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set “one”) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDD2.
ATmega16M1/32M1/64M1 Table 14-11. Overriding Signals for Alternate Functions in PD3..
ATmega16M1/32M1/64M1 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ADC0, Analog to Digital Converter, input channel 0. PCINT26, Pin Change Interrupt 26. • PCINT25/XTAL1/OC0B – Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
ATmega16M1/32M1/64M1 14.4 14.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 SPIPS – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega16M1/32M1/64M1 14.4.8 PORTD – Port D Data Register Bit 14.4.9 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRD – Port D Data Direction Register Bit 14.4.
ATmega16M1/32M1/64M1 15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATmega16M1/32M1/64M1 15.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
ATmega16M1/32M1/64M1 Figure 15-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value.
ATmega16M1/32M1/64M1 Figure 15-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega16M1/32M1/64M1 The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 15.
ATmega16M1/32M1/64M1 non-PWM modes refer to Table 15-2 on page 97. For fast PWM mode, refer to Table 15-3 on page 97, and for phase correct PWM refer to Table 15-4 on page 98. A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 15.7 Modes of Operation The mode of operation, i.e.
ATmega16M1/32M1/64M1 Figure 15-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega16M1/32M1/64M1 PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 15-6.
ATmega16M1/32M1/64M1 feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
ATmega16M1/32M1/64M1 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 15-7 on page 99). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega16M1/32M1/64M1 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 15-10.
ATmega16M1/32M1/64M1 15.9 15.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
ATmega16M1/32M1/64M1 Table 15-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATmega16M1/32M1/64M1 Table 15-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 15-7. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATmega16M1/32M1/64M1 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATmega16M1/32M1/64M1 Table 15-9. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
ATmega16M1/32M1/64M1 • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the “TIFR0 – Timer/Counter 0 Interrupt Flag Register” on page 102.
ATmega16M1/32M1/64M1 16. 16-bit Timer/Counter1 with PWM 16.1 Features • • • • • • • • • • • • 16.2 True 16-bit Design (i.e.
ATmega16M1/32M1/64M1 Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector Tn RTG TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB ICFn (Int.Req.) ICRn TCCRnA Note: 16.2.
ATmega16M1/32M1/64M1 The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
ATmega16M1/32M1/64M1 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
ATmega16M1/32M1/64M1 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle.
ATmega16M1/32M1/64M1 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle.
ATmega16M1/32M1/64M1 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega16M1/32M1/64M1 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit.
ATmega16M1/32M1/64M1 tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 105. The ICF1 output can be used to retrigger the timer counter. It has the same effect than the TOP signal. 16.6.
ATmega16M1/32M1/64M1 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 16.6.4 16.7 Using the Input Capture Unit as TCNT1 Retrigger Input TCNT1 counts from BOTTOM to TOP. The TOP value can be a fixed value, ICR1, or OCR1A. When enabled the Retrigger Input forces to reach the TOP value. It means that ICF1 output is ored with the TOP signal.
ATmega16M1/32M1/64M1 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega16M1/32M1/64M1 16.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega16M1/32M1/64M1 non-PWM modes refer to Table 16-1 on page 124. For fast PWM mode refer to Table 16-2 on page 125, and for phase correct and phase and frequency correct PWM refer to Table 16-3 on page 125. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 16.9 Modes of Operation The mode of operation, i.e.
ATmega16M1/32M1/64M1 Figure 16-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega16M1/32M1/64M1 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
ATmega16M1/32M1/64M1 to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values.
ATmega16M1/32M1/64M1 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11).
ATmega16M1/32M1/64M1 implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega16M1/32M1/64M1 the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction.
ATmega16M1/32M1/64M1 Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
ATmega16M1/32M1/64M1 Figure 16-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega16M1/32M1/64M1 Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 16.11 Register Description 16.11.
ATmega16M1/32M1/64M1 Table 16-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 16-2. Compare Output Mode, Fast PWM(1) COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega16M1/32M1/64M1 Waveform Generation Mode Bit Description(1) Table 16-4.
ATmega16M1/32M1/64M1 When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. • Bit 5 – RTGEN Set this bit to enable the ICP1A as a timer/counter retrigger input. (This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written.
ATmega16M1/32M1/64M1 A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 16.11.
ATmega16M1/32M1/64M1 16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
ATmega16M1/32M1/64M1 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7, 6 – Res: Reserved These bits are reserved and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATmega16M1/32M1/64M1 17. Timer/Counter0 and Timer/Counter1 Prescalers The “8-bit Timer/Counter0 with PWM” and the “16-bit Timer/Counter1 with PWM” share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega16M1/32M1/64M1 Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATmega16M1/32M1/64M1 17.4 17.4.1 Register Description GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 TSM ICPSEL1 – – – – – PSRSYNC Read/Write R/W R/W R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
ATmega16M1/32M1/64M1 18. PSC – Power Stage Controller 18.1 Features • PWM waveform generation function with 6 complementary programmable outputs (able to • • • • • • • 18.
ATmega16M1/32M1/64M1 18.4 PSC Description Figure 18-1.
ATmega16M1/32M1/64M1 The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is able to count up to a top value determined by the contents of POCR_RB register and then according to the selected running mode, count down or reset to zero for another cycle. As can be seen from the block diagram Figure 18-1, the PSC is composed of 3 modules. Each of the 3 PSC modules can be seen as two symetrical entities.
ATmega16M1/32M1/64M1 Figure 18-3. Cycle Presentation in Centered Mode One PSC Cycle PSC Counter Value UPDATE Figure 18-2 and Figure 18-3 graphically illustrate the values held in the PSC counter. Centered Mode is like One Ramp Mode which counts down and then up. Notice that the update of the waveform generator registers is done regardless of ramp Mode at the end of the PSC cycle. 18.5.
ATmega16M1/32M1/64M1 Figure 18-4.
ATmega16M1/32M1/64M1 18.5.3.2 Center Aligned Mode In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered. Figure 18-6.
ATmega16M1/32M1/64M1 Figure 18-7. Controlled Start and Stop Mechanism in Centered Mode POCRnRB POCRnSB POCRnSA PSC Counter 0 Run PSCOUTnA PSCOUTnB Note: See “PCTL – PSC Control Register” on page 151.(PCCYC = 1) 18.6 Update of Values To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the PSC.
ATmega16M1/32M1/64M1 18.7 Overlap Protection Thanks to Overlap Protection two outputs on a same module cannot be active at the same time. So it cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC Overlap Enable). 18.8 Signal Description Figure 18-9.
ATmega16M1/32M1/64M1 18.8.1 Input Description Table 18-1.
ATmega16M1/32M1/64M1 Table 18-4. Internal Outputs IRQPSCn PSC Interrupt Request : two souces, overflow, fault Signal PSCASY ADC Synchronization (+ Amplifier Syncho. )(1) Signal Note: 18.9 Type Width Description Name 1. See “Analog Synchronization” on page 146. PSC Input For detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cookbook’, available on the Atmel web site. Each module 0, 1 and 2 of PSC has its own system to take into account one PSC input.
ATmega16M1/32M1/64M1 outputs. This way needs that CLKPSC is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCINn input can desactivate directly the PSC outputs. Notice that in this case, input is still taken into account as usually by Input Module System as soon as CLKPSC is running. Figure 18-11. PSC Input Filtering CLKPSC Digital Filter 4 x CLK PSC PSC Input Module X 18.9.1.
ATmega16M1/32M1/64M1 18.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing. Figure 18-12. PSC behaviour versus PSCn Input in Mode 001b to 10xb DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTnA PSCOUTnB PSCn Input Figure 18-13. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTnA PSCOUTnB PSCn Input PSCn Input acts indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 18.
ATmega16M1/32M1/64M1 18.12 Analog Synchronization Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB outputs. In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchronization of the ADC. It this case, it’s minimum value is 1. 18.
ATmega16M1/32M1/64M1 Table 18-6. Output Clock versus Selection and Prescaler PCLKSELn PPREn1 PPREn0 CLKPSCn output 0 1 1 CLK I/O / 256 1 0 0 CLK PLL 1 0 1 CLK PLL / 4 1 1 0 CLK PLL / 32 1 1 1 CLK PLL / 256 18.15 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega16M1/32M1/64M1. 18.15.
ATmega16M1/32M1/64M1 When this bit is set, I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveform generator B output and is set and clear according to the PSC operation. • Bit 4 – POEN2A: PSC Output 2A Enable When this bit is clear, I/O pin affected to PSCOUT2A acts as a standard port. When this bit is set, I/O pin affected to PSCOUT2A is connected to the PSC module 2 waveform generator A output and is set and clear according to the PSC operation.
ATmega16M1/32M1/64M1 • Bit 1:0 – PSYNC0[1:0]: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module 0 to the ADC for synchronization . Table 18-8.
ATmega16M1/32M1/64M1 18.16.6 POCRnRBH and POCRnRBL – PSC Output Compare RB Register Bit 7 6 5 4 – – – – 3 2 1 0 POCRnRB[11:8] POCRnRBH POCRnRB[7:0] POCRnRBL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note : n = 0 to 2 according to module number. The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value.
ATmega16M1/32M1/64M1 • Bit 1:0 – Res: Reserved These bits are reserved and will always read as zero. 18.16.8 PCTL – PSC Control Register Bit 7 6 5 4 3 2 1 0 PPRE1 PPRE0 PCLKSEL - - - PCCYC PRUN Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCTL • Bit 7:6 – PPRE1:0 : PSC Prescaler Select This two bits select the PSC input clock division factor. All generated waveform will be modified by this factor. Table 18-11.
ATmega16M1/32M1/64M1 • Bit 6 – PISELn: PSC Module n Input Select Clear this bit to select PSCINn as module n input. Set this bit to select Comparator n output as module n input. • Bit 5 – PELEVn: PSC Module n Input Level Selector When this bit is clear, the low level of selected input generates the significative event for fault function . When this bit is set, the high level of selected input generates the significative event for fault function.
ATmega16M1/32M1/64M1 • Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable When this bit is set, an external event which can generates a fault on module 1 generates also an interrupt. • Bit 1 – PEVE : PSC External Event 0 Interrupt Enable When this bit is set, an external event which can generates a fault on module 0 generates also an interrupt. • Bit 0 – PEOPE: PSC End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle. 18.16.
ATmega16M1/32M1/64M1 19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • 19.
ATmega16M1/32M1/64M1 The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega16M1/32M1/64M1 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 70. Table 19-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega16M1/32M1/64M1 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega16M1/32M1/64M1 Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<
ATmega16M1/32M1/64M1 19.3 19.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega16M1/32M1/64M1 Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 19.5 19.5.
ATmega16M1/32M1/64M1 19.5.2 SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
ATmega16M1/32M1/64M1 Table 19-5. 19.5.
ATmega16M1/32M1/64M1 19.5.4 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission.
ATmega16M1/32M1/64M1 20. CAN – Controller Area Network 20.1 Features • Full CAN Controller • Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B • 6 MOb (Message Object) with their own: – 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B) – 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.
ATmega16M1/32M1/64M1 ically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. 20.3.2 20.3.2.1 Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a length of 11 bits for the identifier, and the CAN extended frame, also known as CAN 2.0 B, supports a length of 29 bits for the identifier.
ATmega16M1/32M1/64M1 20.3.2.2 CAN Extended Frame Figure 20-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier IDT28..18 SOF SRR IDE 18-bit identifier extension ID17..0 RTR r1 Arbitration Field Interframe Space r0 4-bit DLC DLC4..0 15-bit CRC 0 - 8 bytes Control Field Data Field CRC Field CRC ACK del. ACK del. ACK Field 7 bits End of Frame Intermission Bus Idle 3 bits (Indefinite) Interframe Space Remote Frame Bus Idle 11-bit base identifier IDT28..
ATmega16M1/32M1/64M1 Figure 20-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point 20.3.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
ATmega16M1/32M1/64M1 20.3.3.8 Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time. 20.3.3.
ATmega16M1/32M1/64M1 Figure 20-4. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bus Node B wins the bus node B TXCAN CAN bus SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE 20.3.5 --------- Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: 20.3.5.
ATmega16M1/32M1/64M1 20.4 CAN Controller The CAN controller implemented into ATmega16M1/32M1/64M1 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored.
ATmega16M1/32M1/64M1 20.5 20.5.1 CAN Channel Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled, – the input clock is enabled. • Standby mode In standby mode: – the transmitter constantly provides a recessive level (on internal TxCAN) and the receiver is disabled, – input clock is enabled, – the registers and pages remain accessible.
ATmega16M1/32M1/64M1 The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 20-7. Sample and Transmission Point Bit Timing PRS (3-bit length) Sample Point PHS1 (3-bit length) CLK Fcan (Tscl) Time Quantum Prescaler BRP IO Transmission Point PHS2 (3-bit length) SJW (2-bit length) Figure 20-8. General Structure of a Bit Period 1 /CLK IO CLK IO Bit Rate Prescaler Tscl (TQ) F CAN one nominal bit Data Tsyns(5) Notes: 1. 2. 3. 4. 5.
ATmega16M1/32M1/64M1 20.5.3 Baud Rate With no baud rate prescaler (BRP[5..0]=0) the sampling point comes one time quantum too early. This leads to a fail according the ISO16845 Test plan. It is necessary to lengthen the Phase Segment 1 by one time quantum and to shorten the Phase Segment 2 by one time quantum to compensate. The baud rate selection is made by Tbit calculation: Tbit(1) = Tsyns + Tprs + Tphs1 + Tphs2 1. Tsyns = 1 x Tscl = (BRP[5..0]+ 1)/clkIO (= 1TQ) 2. Tprs = (1 to 8) x Tscl = (PRS[2..
ATmega16M1/32M1/64M1 20.6 Message Objects The MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. This means that a MOb has been outlined to allow to describe a CAN message like an object. The set of MObs is the front end part of the “mailbox” where the messages to send and/or to receive are pre-defined as well as possible to decrease the work load of the software. The MObs are independent but priority is given to the lower one in case of multi matching.
ATmega16M1/32M1/64M1 2. The MOb is ready to send a data or a remote frame when the MOb configuration is set (CONMOB). 3. Then, the CAN channel scans all the MObs in Tx configuration, finds the MOb having the highest priority and tries to send it. 4. When the transmission is completed the TXOK flag is set (interrupt). 5. All the parameters and data are available in the MOb until a new initialization. 20.6.2.3 Rx Data & Remote Frame 1.
ATmega16M1/32M1/64M1 1. MObs in frame buffer receive mode need to be initialized as MObs in standard receive mode. 2. The MObs are ready to receive data (or a remote) frames when their respective configurations are set (CONMOB). 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, tries to find the MOb having the highest priority which is matching. 4.
ATmega16M1/32M1/64M1 20.6.4 MOb Page Every MOb is mapped into a page to save place. The page number is the MOb number. This page number is set in CANPAGE register. The other numbers are reserved for factory tests. CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is formatted to provide a direct entry for CANPAGE register. Because CANHPMOB codes CANSIT registers, it will be only updated if the corresponding enable bits (ENRX, ENTX, ENERR) are enabled (c.f. Figure 20-14).
ATmega16M1/32M1/64M1 20.7.1 Prescaler An 8-bit prescaler is initialized by CANTCON register. It receives the clkIO frequency divided by 8. It provides clkCANTIM frequency to the CAN Timer if the CAN controller is enabled. TclkCANTIM = TclkIO x 8 x (CANTCON [7:0] + 1) 20.7.2 16-bit Timer This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When the timer rolls over from 0xFFFF to 0x0000, an interrupt is generated (OVRTIM). 20.7.
ATmega16M1/32M1/64M1 Figure 20-12. Line Error Mode Reset ERRP = 0 BOFF = 0 Error Active TEC > 127 or REC > 127 128 occurrences of 11 consecutive recessive bit TEC < 127 and REC < 127 ERRP = 1 BOFF = 0 ERRP = 0 BOFF = 1 Bus Off Error Passive TEC > 255 interrupt - BOFFIT Note: 20.8.2 More than one REC/TEC change may apply during a given message transfer. Error Types • BERR: Bit error. The bit value which is monitored is different from the bit value sent.
ATmega16M1/32M1/64M1 Figure 20-13. Error Detection Procedures in a Data Frame Arbitration Bit error Stuff error Form error Tx ACK error SOF Rx Identifier RTR Control Message Data CRC CRC ACK ACK del. del. EOF inter. Bit error Stuff error Form error CRC error 20.8.3 Error Setting The CAN channel can detect some errors on the CAN network. • In transmission: The error is set at MOb level. • In reception: - The identified has matched: The error is set at MOb level.
ATmega16M1/32M1/64M1 Figure 20-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX CANSTMOB.6 TXOK[i] CANSTMOB.5 RXOK[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANSTMOB.2 CERR[i] ENRX ENERR CANSIT 1/2 SIT[i] CANIE 1/2 IEMOB[i] 0 CANGIT.7 i CANSTMOB.1 FERR[i] CANSTMOB.0 AERR[i] CANGIT.4 BXOK CANGIT.3 SERG CANGIT.2 CERG CANGIT.1 FERG CANGIT.0 AERG CANIT CANGIE.2 CANGIE.1 CANGIE.6 CANGIE.7 ENERG ENIT ENBX ENBOFF CAN IT CANGIE.0 20.9.2 CANGIT.
ATmega16M1/32M1/64M1 20.10 Register Description Figure 20-15.
ATmega16M1/32M1/64M1 20.10.1 CANGCON – CAN General Control Register Bit 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CANGCON • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request. – 1 - abort request: a reset of CANEN1 and CANEN2 registers is done.
ATmega16M1/32M1/64M1 – 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU.
ATmega16M1/32M1/64M1 • Bit 2 – ENFG: Enable Flag This flag does not generate an interrupt. – 0 - CAN controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode. – 1 - CAN controller enable. • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel. Only entering in bus off mode generates the BOFFIT interrupt. – 0 - no bus off mode. – 1 - bus off mode.
ATmega16M1/32M1/64M1 – 0 - no interrupt. – 1 - burst receive interrupt: set when the frame buffer receive is completed. • Bit 3 – SERG: Stuff Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. • Bit 2 – CERG: CRC Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt.
ATmega16M1/32M1/64M1 • Bit 4 – ENTX: Enable Transmit Interrupt – 0 - interrupt disabled. – 1- transmit interrupt enabled. • Bit 3 – ENERR: Enable MOb Errors Interrupt – 0 - interrupt disabled. – 1- MOb errors interrupt enabled. • Bit 2 – ENBX: Enable Frame Buffer Interrupt – 0 - interrupt disabled. – 1- frame buffer interrupt enabled. • Bit 1 – ENERG: Enable General Errors Interrupt – 0 - interrupt disabled. – 1- general errors interrupt enabled.
ATmega16M1/32M1/64M1 20.10.6 CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers Bit 7 6 5 4 3 2 1 0 - - IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 CANIE2 - - - - - - - - CANIE1 Bit 15 14 13 12 11 10 9 8 R/W Read/Write R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 5:0 - IEMOB[5:0]: Interrupt Enable by MOb – 0 - interrupt disabled.
ATmega16M1/32M1/64M1 • Bit 6:1 – BRP[5:0]: Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. BRP[5:0] + 1 Tscl = clkIO frequency If ‘BRP[5..0]=0’, see Section 20.5.3 “Baud Rate” on page 173 and Section • “Bit 0 – SMP: Sample Point(s)” on page 190. • Bit 0 – Res: Reserved This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. 20.10.
ATmega16M1/32M1/64M1 20.10.10 CANBT3 – CAN Bit Timing Register 3 Bit 7 6 5 4 3 2 1 0 - PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP Read/Write - R/W R/W R/W R/W R/W R/W R/W Initial Value - 0 0 0 0 0 0 0 CANBT3 • Bit 7– Res: Reserved This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • Bit 6:4 – PHS2[2:0]: Phase Segment 2 This phase is used to compensate for phase edge errors.
ATmega16M1/32M1/64M1 20.10.12 CANTIML and CANTIMH – CAN Timer Registers Bit 7 6 5 4 3 2 1 0 CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 CANTIML CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 15:0 - CANTIM[15:0]: CAN Timer Count CAN timer counter range 0 to 65,535. 20.10.
ATmega16M1/32M1/64M1 • Bit 3:0 – CGP[3:0]: CAN General Purpose Bits These bits can be pre-programmed to match with the wanted configuration of the CANPAGE register (i.e., AINC and INDX2:0 setting). 20.10.
ATmega16M1/32M1/64M1 • Bit 4 – BERR: Bit Error (Only in Transmission) This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The bit value monitored is different from the bit value sent. Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. • Bit 3 – SERR: Stuff Error This flag can generate an interrupt.
ATmega16M1/32M1/64M1 These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication. • This operation is necessary to be able to reset the BXOK flag. • This operation also set the corresponding bit in the CANEN registers. • Bit 5 – RPLV: Reply Valid Used in the automatic reply mode after receiving a remote frame. – 0 - reply not ready. – 1 - reply ready and valid.
ATmega16M1/32M1/64M1 • Bit 31:21 – IDT[10:0]: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 20:3 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when CANIDTn are written. When a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values.
ATmega16M1/32M1/64M1 20.11.4 CANIDM1, CANIDM2, CANIDM3, and CANIDM4 – CAN Identifier Mask Registers V2.
ATmega16M1/32M1/64M1 • Bit 2 – RTRMSK: Remote Transmission Request Mask – 0 - comparison true forced – 1 - bit comparison enabled. • Bit 1 – Reserved Bit Writing zero in this bit is recommended. • Bit 0 – IDEMSK: Identifier Extension Mask – 0 - comparison true forced – 1 - bit comparison enabled. 20.11.
ATmega16M1/32M1/64M1 Table 20-2. fCLKIO (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies CAN Rate (Kbps) 1000 Description Sampling Point 69 % (1) 75 % 500 75 % 250 75 % 200 75 % 125 75 % 100 75 % 1000 67 % (1) 500 75 % 250 75 % 200 75 % 125 75 % 100 75 % 16.000 12.000 Segments Registers TQ (µs) Tbit (TQ) Tprs (TQ) Tph1 (TQ) Tph2 (TQ) Tsjw (TQ) CANBT1 CANBT2 CANBT3 0.0625 16 7 4 4 1 0x00 0x0C 0x36 (2) 0.
ATmega16M1/32M1/64M1 Table 20-2. fCLKIO (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) CAN Rate (Kbps) 1000 500 250 Description Sampling Point 63 % (1) TQ (µs) Segments Tbit (TQ) Note: data- - - 1 0x00 0x04 0x12 (2) 69 % (1) 0.125 16 7 4 4 1 0x00 0x0C 0x36 (2) 75 % 0.250 8 3 2 2 1 0x02 0x04 0x13 0.250 16 7 4 4 1 0x02 0x0C 0x37 75 % 75 % 100 75 % 0.500 8 3 2 2 1 0x06 0x04 0x13 0.250 20 8 6 5 1 0x02 0x0E 0x4B 0.
ATmega16M1/32M1/64M1 21. LIN / UART - Local Interconnect Network Controller or UART 21.1 21.1.1 Features LIN • Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility) • Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow Concept” 21.1.2 21.2 • • • • • • • of LIN 2.
ATmega16M1/32M1/64M1 21.3 21.3.1 LIN Protocol Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. Figure 21-1. LIN cluster with one master node and “n” slave nodes master node master task slave node 1 slave node n slave task slave task slave task LIN bus The master task decides when and which frame shall be transferred on the bus.
ATmega16M1/32M1/64M1 21.3.3 Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. • Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always present at the same position in the data field for all frames with the same identifier. • Diagnostic messages Diagnostic messages are transported in frames with two reserved identifiers.
ATmega16M1/32M1/64M1 21.4.1 LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software application structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f. Section 21.3.4 on page 202). The ATmega16M1/32M1/64M1 conforms to this perspective. The only link between the master task and the slave task will be at the cross-over point where the interrupt routine is called once a new identifier is available.
ATmega16M1/32M1/64M1 21.4.3 LIN/UART Controller Structure Figure 21-4. LIN/UART Controller Block Diagram CLK IO RxD Finite State Machine Prescaler Sample /bit FSM BAUD_RATE Get Byte RX Put Byte TX Frame Time-out TxD Synchronization Monitoring Data FIFO 21.4.4 BUFFER LIN/UART Command Overview Figure 21-5.
ATmega16M1/32M1/64M1 Table 21-1. LIN/UART Command List LENA LCMD[2] LCMD[1] LCMD[0] Command 0 x x x Disable peripheral 0 Rx Header - LIN abort LIN withdrawal 1 Tx Header LCMD[2..0]=000 after Tx 0 Rx Response LCMD[2..0]=000 after Rx 1 Tx Response LCMD[2..0]=000 after Tx 0 0 Byte transfer 1 0 Rx Byte 0 1 Tx Byte 1 1 Full duplex 0 0 1 1 1 Comment no CRC, no Time out LTXDL=LRXDL=0 (LINDLR: read only register) 21.4.
ATmega16M1/32M1/64M1 21.4.6.2 Tx Header Function In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LINBTR registers). The controller is responsible for: • The transmission of the BREAK field - 13 dominant bits, • The transmission of the SYNCH field - character 0x55, • The transmission of the PROTECTED IDENTIFIER field.
ATmega16M1/32M1/64M1 21.4.6.4 Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. “Data Management” on page 217). Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access. 21.4.7 UART Commands Setting the LCMD[2] bit in LINENR register enables UART commands.
ATmega16M1/32M1/64M1 21.5 21.5.1 LIN / UART Description Reset The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit performs a partial reset as shown in Table 21-2. Table 21-2. 21.5.2 Reset of LIN/UART Registers Register Name Reset Value LSWRES Value LIN Control Reg. LINCR 0000 0000 b 0000 0000 b LIN Status & Interrupt Reg.
ATmega16M1/32M1/64M1 Table 21-3. Mode Configuration Table versus Mode LCONF[1..0] Configuration 00 b 8-bit data, no parity & 1 stop-bit 01 b 8-bit data, even parity & 1 stop-bit 10 b 8-bit data, odd parity & 1 stop-bit 11 b Listening mode, 8-bit data, no parity & 1 stop-bit UART The LIN configuration is independent of the programmed LIN protocol. The listening mode connects the internal Tx LIN and the internal Rx LIN together.
ATmega16M1/32M1/64M1 When the busy signal is set, some registers are locked, user writing is not allowed: • “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES, • “LIN Baud Rate Registers” - LINBRRL & LINBRRH, • “LIN Data Length Register” - LINDLR, • “LIN Identifier Register” - LINIDR, • “LIN Data Register” - LINDAT. If the busy signal is set, the only available commands are: • LCMD[1..
ATmega16M1/32M1/64M1 The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be reset to 32 for the next header. The LINBTR register can be used to re-calibrate the clock oscillator. The re-synchronization is not performed if the LIN node is enabled as a master. 21.5.6.3 Handling LBT[5:0] LDISR bit of LINBTR register is used to: • To enable the setting of LBT[5:0] (to manually adjust the baud rate especially in the case of UART mode).
ATmega16M1/32M1/64M1 21.5.7.2 Data Length in LIN 1.3 • LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL). • Via the above mechanism, a length of 0 or >8 is not possible. 21.5.7.3 Data Length in Rx Response Figure 21-9. LIN2.
ATmega16M1/32M1/64M1 • The user initializes LTXDL field before setting the Tx Response command, • After setting the Tx Response command, LRXDL is reset by hardware, • LTXDL will remain unchanged during Tx (during busy signal), • LRXDL will count the number of transmitted bytes (during busy signal), • If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes without error, • If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LT
ATmega16M1/32M1/64M1 21.5.9 xxERR Flags LERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see Section 21.5.13 “Interrupts” on page 216). There are eight flags: • LBERR = LIN Bit ERRor. A unit that is sending a bit on the bus also monitors the bus. A LIN bit error will be flagged when the bit value that is monitored is different from the bit value that is sent. After detection of a LIN bit error the transmission is aborted. • LCERR = LIN Checksum ERRor.
ATmega16M1/32M1/64M1 Figure 21-12. LIN timing and frame time-out T Frame T Header T Response PROTECTED IDENTIFIER SYNC BREAK Field Field DATA-0 Field DATA-n Field CHECKSUM Field Field Nominal T Header_Nominal T Response_Nominal T Frame_Nominal = 34 x T Bit T Bit T Response_Nominal = 10 ( Number_of_Data + 1 ) x = T Header_Nominal + Maximun T Header_Maximum T Response_Maximum T Frame_Maximum 21.5.11 = = = before Time-out T Header_Nominal 1.
ATmega16M1/32M1/64M1 21.5.13 Interrupts As shown in Figure 21-13 on page 216, the four communication flags of the LINSIR register are combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register. (see Section 21.5.8 “xxOK Flags” on page 213 and Section 21.5.9 “xxERR Flags” on page 214). Figure 21-13. LIN Interrupt Mapping LINERR.7 LABORT LINERR.6 LTOERR LINERR.5 LOVERR LINSIR.3 LINERR.4 LFERR LIN ERR LERR LINERR.3 LSERR LINENIR.3 LINENIR.
ATmega16M1/32M1/64M1 21.5.15 21.5.15.1 Data Management LIN FIFO Data Buffer To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the LINDAT register. LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can be read or written. The data index is automatically incremented after each LINDAT access if the LAINC (active low) bit is cleared.
ATmega16M1/32M1/64M1 10. LINDAT: - All bits are in R/W accessible, - Note that LAINC has no more effect on the auto-incrementation and the access to the full FIFO is done setting LINDX[2..0] of LINSEL. Note: 21.6 21.6.1 When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and further communication may be corrupted.
ATmega16M1/32M1/64M1 • Bit 3 - LENA: Enable – 0 = Disable (both LIN and UART modes), – 1 = Enable (both LIN and UART modes). • Bit 2:0 - LCMD[2:0]: Command and mode The command is only available if LENA is set, and is set according to Table 21-7. Table 21-7. 21.6.
ATmega16M1/32M1/64M1 The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits. In UART mode, this bit is also cleared by reading LINDAT. • Bit 2 - LIDOK: Identifier Interrupt This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR. – 0 = No identifier, – 1 = Slave task: Identifier present, master task: Tx Header complete. The user clears this bit by writing 1, in order to reset this interrupt.
ATmega16M1/32M1/64M1 – 1 = Transmit performed interrupt enabled. • Bit 0 - LENRXOK: Enable Receive Performed Interrupt – 0 = Receive performed interrupt masked, – 1 = Receive performed interrupt enabled. 21.6.4 LINERR – LIN Error Register Bit 7 6 5 4 3 2 1 0 LABORT LTOERR LOVERR LFERR LSERR LPERR LCERR LBERR Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 LINERR • Bit 7 - LABORT: Abort Flag – 0 = No warning, – 1 = LIN abort command occurred.
ATmega16M1/32M1/64M1 This bit is cleared when LERR bit in LINSIR is cleared. • Bit 0 - LBERR: Bit Error Flag – 0 = no error, – 1 = Bit error. This bit is cleared when LERR bit in LINSIR is cleared. 21.6.
ATmega16M1/32M1/64M1 • Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max). In UART mode this field is unused. • Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max). In UART mode this field is unused. 21.6.
ATmega16M1/32M1/64M1 • Bits 7:4 - Res: Reserved These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written. • Bit 3 - LAINC: Auto Increment of Data Buffer Index In LIN mode: – 0 = Auto incrementation of FIFO data buffer index (default), – 1 = No auto incrementation. In UART mode this field is unused. • Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index In LIN mode: location (index) of the LIN response data byte into the FIFO data buffer.
ATmega16M1/32M1/64M1 22. ADC – Analog to Digital Converter 22.1 Features • • • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 8- 250 µs Conversion Time Up to 120 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels 3 Differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40 Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega16M1/32M1/64M1 Figure 22-1. Analog to Digital Converter Block Schematic Current Source ISRCEN AREF / ISRC ISRC AREFEN AVCC Internal 2.
ATmega16M1/32M1/64M1 22.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
ATmega16M1/32M1/64M1 Figure 22-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega16M1/32M1/64M1 When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference Selection” on page 230 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 3.
ATmega16M1/32M1/64M1 Figure 22-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 Next Conversion 8 11 12 13 14 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 22-7.
ATmega16M1/32M1/64M1 If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
ATmega16M1/32M1/64M1 AREF pin is alternate function with ISRC Current Source output. When current source is selected, the AREF pin is not connected to the internal reference voltage network. See AREFEN and ISRCEN bits in Section “ADCSRB – ADC Control and Status Register B”, page 246. If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 29-5 on page 319. 22.
ATmega16M1/32M1/64M1 to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 22-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 22.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1.
ATmega16M1/32M1/64M1 22.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected. (See “AMP0CSR – Amplifier 0 Control and Status register” on page 249., See “AMP1CSR – Amplifier 1 Control and Status register” on page 250.
ATmega16M1/32M1/64M1 Figure 22-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 22-12.
ATmega16M1/32M1/64M1 Figure 22-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATmega16M1/32M1/64M1 (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive. Figure 22-14 shows the decoding of the differential input range. Table 22-2 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a reference voltage of VREF. Figure 22-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /Gain 0 0x3FF VREF/Gain Differential Input Voltage (Volts) 0x200 Table 22-2.
ATmega16M1/32M1/64M1 Example 1: – ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 – ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: – ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ATmega16M1/32M1/64M1 The measured voltage has a linear relationship to the temperature as described in Table 22-3 on page 239. The voltage sensitivity is approximately 1 mV/°C and the accuracy of the temperature measurement is +/- 10°C after bandgap calibration. Table 22-3. Temperature vs. Sensor Output Voltage (Typical Case) Temperature / °C -40 °C +25 °C +85 °C Voltage / mV 600 mV 762 mv TBD mV The values described in Table 22-3 on page 239 are typical values.
ATmega16M1/32M1/64M1 Amplified conversions can be synchronized to PSC events (See “Synchronization Source Description in One Ramp Mode” on page 149 and “Synchronization Source Description in Centered Mode” on page 149) or to the internal clock CK ADC equal to eighth the ADC clock frequency. In case the synchronization is done the ADC clock divided by 8, this synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CKADC2.
ATmega16M1/32M1/64M1 Figure 22-16.
ATmega16M1/32M1/64M1 Figure 22-17.
ATmega16M1/32M1/64M1 Figure 22-18.
ATmega16M1/32M1/64M1 22.10 Register Description The ADC of the ATmega16M1/32M1/64M1 is controlled through 3 different registers. The ADCSRA and the ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which allows to select the VREF source and the channel to be converted. The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and AMP1CSR. Then the start of conversion is done via the ADC control and status registers.
ATmega16M1/32M1/64M1 22.10.2 Bit 4: 0 – MUX[4:0]: ADC Channel Selection Bits These 4 bits determine which analog inputs are connected to the ADC input. The different setting are shown in Table 22-5. Table 22-5.
ATmega16M1/32M1/64M1 • Bit 6 – ADSC: ADC Start Conversion Bit Set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect. The first conversion performs the initialization of the ADC. • Bit 5 – ADATE: ADC Auto trigger Enable Bit Set this bit to enable the auto triggering mode of the ADC. Clear it to return in single conversion mode.
ATmega16M1/32M1/64M1 • Bit 6 – ISRCEN: Current Source Enable Set this bit to source a 100µA current to the AREF pin. Clear this bit to use AREF pin as Analog Reference pin. • Bit 5 – AREFEN: Analog Reference pin Enable Set this bit to connect the internal AREF circuit to the AREF pin. Clear this bit to disconnect the internal AREF circuit from the AREF pin. • Bit 4 – Res: Reserved This bit is reserved and will always read as zero.
ATmega16M1/32M1/64M1 Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH. Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read ADCH to have the conversion result. 22.10.5.1 ADLAR = 0 Bit Read/Write Initial Value 22.10.5.
ATmega16M1/32M1/64M1 • Bit 6:0 – ADC10D..8D, ACMP0D, ACMP1D, ACMP3D, AMP0PD, AMP0ND, AMP1PD, AMP1ND, AMP2PD: ADC10..8, ACMP0, ACMP1, ACMP3, AMP0P, AMP0N, AMP1P, AMP1N, AMP2P Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
ATmega16M1/32M1/64M1 Table 22-9. 22.10.
ATmega16M1/32M1/64M1 • Bit 3 – AMPCMP1: Amplifier 1 - Comparator 1 connection Set this bit to connect the amplifier 1 to the comparator 1 positive input. In this configuration the comparator clock is adapted to the amplifier clock and AMP1TS2,AMP1TS1, AMP1TS0 bits have no effect. Clear this bit to normally use the Amplifier 1. • Bit 2:0 – AMP1TS[2:0]: Amplifier 1 Clock Source Selection Bits In accordance with the Table 22-11, these 3 bits select the event which will generate the clock for the amplifier 1.
ATmega16M1/32M1/64M1 These 2 bits determine the gain of the amplifier 2. The different setting are shown in Table 22-12. Table 22-12. Amplifier 2 Gain Selection AMP2G[1:0] Description 00 Gain 5 01 Gain 10 10 Gain 20 11 Gain 40 To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 Amplifier synchronization clock periods.
ATmega16M1/32M1/64M1 23. ISRC - Current Source 23.1 Features • 100µA Constant current source • ± 2% Absolute Accuracy The ATmega16M1/32M1/64M1 features a 100µA ±2% Current Source. After RESET or up on request, the current is flowing through an external resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using a resistor in serie with a ≤0.5% tolerance is recommended.
ATmega16M1/32M1/64M1 ATmega16M1/32M1/64M1 proposes to have an external resistor used in conjunction with the Current Source. The device measures the voltage to the boundaries of the resistance via the Analog to Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. In automotive applications, distributed voltages are very disturbed.
ATmega16M1/32M1/64M1 23.2.2 Voltage Reference for External Devices An external resistor used in conjunction with the Current Source can be used as voltage reference for external devices. Using a resistor in serie with a lower tolerance than the Current Source accuracy (≤2%) is recommended. Table 23-2 gives an example of voltage references using standard values of resistors. 23.2.
ATmega16M1/32M1/64M1 24. AC – Analog Comparator 24.1 Features • • • • • 24.2 4 Analog Comparators High Speed Clocked Comparators +/-30mV Hysteresys 4 reference levels Generation of Configurable Interrupts Overview The ATmega16M1/32M1/64M1 features 4 fast analog comparators. The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx.
ATmega16M1/32M1/64M1 Figure 24-1.
ATmega16M1/32M1/64M1 24.3 Use of ADC Amplifiers Thanks to AMPCMP0 configuration bit, Comparator 0 positive input can be connected to Amplifier O output. In that case, the clock of comparator 0 is adapted to the amplifier 0 clock. See “AMP0CSR – Amplifier 0 Control and Status register” on page 249. Thanks to AMPCMP1 configuration bit, Comparator 1 positive input can be connected to Amplifier 1 output. In that case, the clock of comparator 1 is adapted to the amplifier 1 clock.
ATmega16M1/32M1/64M1 Table 24-2. 24.4.2 Analog Comparator 0 negative input selection AC0M[2:0] Description 000 “Vref”/6.40 001 “Vref”/3.20 010 “Vref”/2.13 000 “Vref”/1.60 111 Bandgap (1.
ATmega16M1/32M1/64M1 In case ICES1 bit (“TCCR1B – Timer/Counter1 Control Register B” on page 126) is set high, the rising edge of AC1O is the capture/trigger event of the Timer/Counter1, in case ICES1 is set to zero, it is the falling edge which is taken into account. Clear this bit to disable this function. In this case, no connection between the Analog Comparator and the input capture function exists.
ATmega16M1/32M1/64M1 Table 24-5. Interrupt sensitivity selection AC2IS[1:0] Description 00 Comparator Interrupt on output toggle 01 Reserved 10 Comparator interrupt on output falling edge 11 Comparator interrupt on output rising edge • Bit 3 – Res: Reserved This bit is reserved and will always read as zero. • Bit 2:0– AC2M[2:0]: Analog Comparator 2 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 24-6.
ATmega16M1/32M1/64M1 . Table 24-7. Interrupt sensitivity selection AC3IS[1:0] Description 00 Comparator Interrupt on output toggle 01 Reserved 10 Comparator interrupt on output falling edge 11 Comparator interrupt on output rising edge • Bit 3 – Res: Reserved This bit isreserved and will always read as zero. • Bit 2:0– AC3M[2:0]: Analog Comparator 3 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 24-6.
ATmega16M1/32M1/64M1 AC2IE in AC2CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 5 – AC1IF: Analog Comparator 1 Interrupt Flag Bit This bit is set by hardware when comparator 1 output event triggers off the interrupt mode defined by AC1IS1 and AC1IS0 bits in AC1CON register. This bit is cleared by hardware when the corresponding interrupt vector is executed in case the AC1IE in AC1CON register is set.
ATmega16M1/32M1/64M1 24.4.7 DIDR1 – Digital Input Disable Register 1 Bit 7 6 5 4 3 2 1 0 - AMP2PD ACMP0D AMP0PD AMP0ND ADC10D ACMP1D ADC9D AMP1PD ACMP3D ADC8D AMP1ND Read/Write - - R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR1 • Bit 5, 2, 1: ACMP0D, ACMP1PD, ACMP3PD: ACMP0, ACMP1P, ACMP3P Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is disabled.
ATmega16M1/32M1/64M1 25. DAC – Digital to Analog Converter 25.1 Features • • • • • 10 bits resolution 8 bits linearity +/- 0.5 LSB accuracy between 100mV and AVcc-100mV Vout = DAC*Vref/1023 The DAC could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver. • The output impedance of the driver is around 100 Ohms. So the driver is able to load a 1nF capacitance in parallel with a resistor higher than 33K with a time constant around 1us. 25.
ATmega16M1/32M1/64M1 Figure 25-1. Digital to Analog Converter Block Schematic DAC Result D2A pin VRef DAC Output Driver 10 1 0 10 10 DAC High bits DAC Low bits Sources DACH Update DAC Trigger Edge Detector DAATE DACL DATS2 DATS1 DATS0 - DALA DAOE DAEN DACON 25.3 Operation The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value.
ATmega16M1/32M1/64M1 25.4 Starting a Conversion The DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON register is set, the DAC converts the value present on the DACH and DACL registers in accordance with the register DACON setting. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the DAC Auto Trigger Enable bit, DAATE in DACON.
ATmega16M1/32M1/64M1 • Bit 6:4 – DATS[2:0]: DAC Trigger Selection bits These bits are only necessary in case the DAC works in auto trigger mode. It means if DAATE bit is set. In accordance with the Table 25-1, these 3 bits select the interrupt event which will generate the update of the DAC input values. The update will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. Table 25-1.
ATmega16M1/32M1/64M1 25.5.2.1 DALA = 0 Bit Read/Write Initial Value 25.5.2.
ATmega16M1/32M1/64M1 26. debugWIRE On-chip Debug System 26.1 Features • • • • • • • • • • 26.
ATmega16M1/32M1/64M1 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 26.
ATmega16M1/32M1/64M1 27. Boot Loader Support – Read-While-Write Self-Programming • • • • • • • • Features Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 27.1 1. A page is a section in the Flash consisting of several bytes (see Table 28-9 on page 294) used during programming.
ATmega16M1/32M1/64M1 27.3 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega16M1/32M1/64M1 Figure 27-1. Read-While-Write vs.
ATmega16M1/32M1/64M1 Figure 27-2.
ATmega16M1/32M1/64M1 Table 27-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega16M1/32M1/64M1 Table 27-4. BOOTRST Note: 27.6 Boot Reset Fuse(1) Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 27-10 on page 285) 1. “1” means unprogrammed, “0” means programmed Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
ATmega16M1/32M1/64M1 Figure 27-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 27.7 1. The different variables used in Figure 27-3 are listed in Table 27-12 on page 285. Self-Programming the Flash The program memory is updated in a page by page fashion.
ATmega16M1/32M1/64M1 27.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
ATmega16M1/32M1/64M1 the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 282 for an example. 27.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega16M1/32M1/64M1 the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 28-6 on page 292 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer.
ATmega16M1/32M1/64M1 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
ATmega16M1/32M1/64M1 brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega16M1/32M1/64M1 27.7.14 ATmega16M1 - 16K - Flash Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-7.
ATmega16M1/32M1/64M1 27.7.15 ATmega32M1 - 32K - Flash Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-10.
ATmega16M1/32M1/64M1 27.7.16 ATmega64M1 - 64K - Flash Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-13.
ATmega16M1/32M1/64M1 27.8 27.8.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega16M1/32M1/64M1 destination register. See “Reading the Fuse and Lock Bits from Software” on page 280 for details. • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
ATmega16M1/32M1/64M1 28. Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega16M1/32M1/64M1 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1.
ATmega16M1/32M1/64M1 Table 28-3. Lock Bit Protection Modes(1)(2). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega16M1/32M1/64M1 Table 28-4. Extended Fuse Byte Extended Fuse Byte Description Default Value BODLEVEL2(1) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1(1) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(1) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 28.3 Bit No 1. See Table 29-3 on page 313 for BODLEVEL Fuse decoding.
ATmega16M1/32M1/64M1 Table 28-5. PSC Output Behavior During and after Reset until POC register is written PSCRB PSCARV PSCBRV PSCOUTnA PSCOUTnB BODLEVEL2(1) 2 Brown-out Detector trigger level 1 (unprogramme d) BODLEVEL1(1) 1 Brown-out Detector trigger level 1 (unprogramme d) BODLEVEL0(1) 0 Brown-out Detector trigger level 1 (unprogramme d) Table 28-6.
ATmega16M1/32M1/64M1 Notes: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 9-9 on page 34 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 9-9 on page 34 for details. 3. The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock Output Buffer” on page 34 for details. 4. See “System Clock Prescaler” on page 34 for details. The status of the Fuse bits is not affected by Chip Erase.
ATmega16M1/32M1/64M1 28.6 Page Size Table 28-9. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega16M1 8K words (16K bytes) 64 words (128 bytes) PC[5:0] 128 PC[12:6] 12 ATmega32M1 16K words (32K bytes) 64 words (128 bytes) PC[5:0] 256 PC[13:6] 13 ATmega64M1 32K words (64K bytes) 128 words (256 bytes) PC[6:0] 256 PC[14:7] 14 Table 28-10. No. of Words in a Page and No. of Pages in the EEPROM 28.
ATmega16M1/32M1/64M1 Figure 28-1. Parallel Programming + 5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 VCC XA1 PAGEL + 12 V + 5V AVCC PB[7:0] PD6 DATA PD7 RESET BS2 PE2 XTAL1 GND Table 28-11.
ATmega16M1/32M1/64M1 Table 28-13. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 28-14. Command Byte Bit Coding Command Byte 28.
ATmega16M1/32M1/64M1 If the rise time of the Vcc is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 1. Set Prog_enable pins listed in Table 28-12 to “0000”, RESET pin to “0” and Vcc to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Monitor Vcc, and as soon as Vcc reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET. 4.
ATmega16M1/32M1/64M1 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D.
ATmega16M1/32M1/64M1 Figure 28-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 28-9 on page 294. Figure 28-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
ATmega16M1/32M1/64M1 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 28-4 for signal waveforms). Figure 28-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR.
ATmega16M1/32M1/64M1 28.9.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 297 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 28.9.
ATmega16M1/32M1/64M1 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 28.9.
ATmega16M1/32M1/64M1 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 28.9.15 Parallel Programming Characteristics Figure 28-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 28-8.
ATmega16M1/32M1/64M1 Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 28-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 28-16.
ATmega16M1/32M1/64M1 Table 28-16. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 28.
ATmega16M1/32M1/64M1 28.10.1 Serial Programming Algorithm When writing serial data to the ATmega16M1/32M1/64M1, data is clocked on the rising edge of SCK. When reading data from the ATmega16M1/32M1/64M1, data is clocked on the falling edge of SCK. See Figure 28-11 for timing details. To program and verify the ATmega16M1/32M1/64M1 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 28-18): 1.
ATmega16M1/32M1/64M1 28.10.3 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
ATmega16M1/32M1/64M1 Table 28-18. Serial Programming Instruction Set (Continued) Instruction Format Instruction Write EEPROM Memory Load EEPROM Memory Page (page access) Write EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Byte4 1100 0000 000x xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page.
ATmega16M1/32M1/64M1 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega16M1/32M1/64M1 TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition IIL Input Leakage Current I/O Pin IIH Input Leakage Current I/O Pin RRST Reset Pull-up Resistor Rpu I/O Pin Pull-up Resistor Min. Typ. Max. Units VCC = 5.5V, pin low (absolute value) 50 nA VCC = 5.5V, pin high (absolute value) 50 nA 30 200 kΩ 20 50 kΩ Active 8 MHz, VCC = 3V, RC osc, PRR = 0xFF 3.
ATmega16M1/32M1/64M1 5. Minimum VCC for Power-down is 2.5V. 6. The Analog Comparator Propogation Delay equals 1 comparator clock plus 30 nS. See “AC – Analog Comparator” on page 256. for comparator clock definition. 29.3 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 29-1 , the Maximum Frequency vs. VCC is linear between 2.7V and 4.5V. Figure 29-1. Maximum Frequency vs. VCC 16MHz 8MHz Safe Operating Area 2.7V 4.5V 5.
ATmega16M1/32M1/64M1 29.4 29.4.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 29-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±1% User Calibration 7.3 - 8.1 MHz 2.7V - 5.5V -40°C to +85°C ±10% 29.5 External Clock Drive Characteristics Figure 29-2. External Clock Drive Waveforms V IH1 V IL1 Table 1. External Clock Drive VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min.
ATmega16M1/32M1/64M1 29.6 System and Reset Characteristics Table 29-2. Symbol VPOT Reset, Brown-out(1) and Internal Voltage(1) Characteristics Parameter Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.7 V Power-on Reset Threshold Voltage (falling)(2) 0.8 0.9 1.6 V 0.4 V VPORMAX VCC Max. start voltage to ensure internal Power-on Reset signal VPORMIN VCC Min. start voltage to ensure internal Power-on Reset signal -0.
ATmega16M1/32M1/64M1 29.7 PLL Characteristics . Table 2. PLL Characteristics - VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Min. Typ. Max. Units PLLIF Input Frequency 0.5 1 2 MHz PLLF PLL Factor PLLLT Lock-in Time 64 µS Note: 29.8 64 While connected to external clock or external oscillator, PLL Input Frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC...
ATmega16M1/32M1/64M1 Figure 29-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 29-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega16M1/32M1/64M1 29.9 ADC Characteristics Table 29-4. Symbol ADC Characteristics - TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted) Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 2.56V ADC clock = 500 kHz 2.5 LSB Single Ended Conversion VREF = 2.56V ADC clock = 1MHz 6 LSB Resolution Absolute accuracy Single Ended Conversion VREF = 2.
ATmega16M1/32M1/64M1 Table 29-4. Symbol ADC Characteristics - TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Parameter Condition Min Typ Max Units Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -4 0 LSB Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -2 2.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -0.5 0.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -0.5 0.
ATmega16M1/32M1/64M1 29.10 Parallel Programming Characteristics Figure 29-5. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 29-6.
ATmega16M1/32M1/64M1 Figure 29-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) ADDR1 (Low Byte) DATA (High Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 29-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 29-5.
ATmega16M1/32M1/64M1 Table 29-5. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Min. Max. Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ. 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATmega16M1/32M1/64M1 30.
ATmega16M1/32M1/64M1 31.
ATmega16M1/32M1/64M1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved – – – – – – – – Page (0xBD) Reserved – – – – – – – – (0xBC)(5) PIFR – – – – PEV2 PEV1 PEV0 PEOP page 153 (0xBB)(5) PIM – – – – PEVE2 PEVE1 PEVE0 PEOPE page 152 (0xBA)(5) PMIC2 POVEN2 PISEL2 PELEV2 PFLTE2 PAOC2 PRFM22 PRFM21 PRFM20 page 151 (0xB9)(5) PMIC1 POVEN1 PISEL1 PELEV1 PFLTE1 PAOC1 PRFM12 PRFM11 PRFM10 page 151 (0xB8)(5) PMIC0 P
ATmega16M1/32M1/64M1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 244 (0x7B) ADCSRB ADHSM ISRCEN AREFEN – ADTS3 ADTS2 ADTS1 ADTS0 page 246 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 245 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 247 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC
ATmega16M1/32M1/64M1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 26 0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 26 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) Reserved – – – – – – – – 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 130 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A
ATmega16M1/32M1/64M1 32.
ATmega16M1/32M1/64M1 Mnemonics Operands Description Operation Flags BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None #Clocks 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd
ATmega16M1/32M1/64M1 Mnemonics Operands Description Operation Flags #Clocks POP Rd Pop Register from Stack Rd ← STACK None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: 1.
ATmega16M1/32M1/64M1 33. Errata 33.1 Errata ATmega16M1 The revision letter in this section refers to revisions of the ATmega16M1 device. 33.1.1 Rev. A Not samplet 33.2 Errata ATmega32M1 The revision letter in this section refers to revisions of the ATmega32M1 device. 33.2.1 Rev. A Not samplet 33.3 Errata ATmega64M1 The revision letter in this section refers to revisions of the ATmega64M1 device. 33.3.1 Rev.
ATmega16M1/32M1/64M1 34. Ordering Information 34.1 ATmega16M1 Speed 16MHz Note: Power Supply 2.7 - 5.5V Ordering Code Package Operation Range ATmega16M1 - AU 32A ATmega16M1 - MU 32M1-A Industrial (-40°C to 85°C) All packages are Pb free, fully LHF Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.
ATmega16M1/32M1/64M1 34.2 Note: ATmega32M1 Speed Power Supply 16MHz 2.7 - 5.5V Ordering Code Package Operation Range ATmega32M1 - AU 32A ATmega32M1 - MU 32M1-A Industrial (-40°C to 85°C) All packages are Pb free, fully LHF Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.
ATmega16M1/32M1/64M1 34.3 Note: ATmega64M1 Speed Power Supply 16MHz 2.7 - 5.5V Ordering Code Package Operation Range ATmega64M1 - AU 32A ATmega64M1 - MU 32M1-A Industrial (-40°C to 85°C) All packages are Pb free, fully LHF Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.
ATmega16M1/32M1/64M1 35. Packaging Information 35.1 32A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion.
ATmega16M1/32M1/64M1 35.2 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig.
ATmega16M1/32M1/64M1 36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 8209A – 08/09 1. Initial revision.
ATmega16M1/32M1/64M1 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Pin Descriptions .................................................................................................3 Overview ................................................................................................... 5 2.
ATmega16M1/32M1/64M1 9.5 Calibrated Internal RC Oscillator .....................................................................31 9.6 PLL ..................................................................................................................32 9.7 128 kHz Internal Oscillator ..............................................................................33 9.8 External Clock .................................................................................................33 9.
ATmega16M1/32M1/64M1 15 8-bit Timer/Counter0 with PWM ............................................................ 86 15.1 Features ..........................................................................................................86 15.2 Overview ..........................................................................................................86 15.3 Timer/Counter Clock Sources .........................................................................87 15.4 Counter Unit ..............
ATmega16M1/32M1/64M1 18.8 Signal Description ..........................................................................................141 18.9 PSC Input ......................................................................................................143 18.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing. 145 18.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action ....................145 18.12 Analog Synchronization .........................................
ATmega16M1/32M1/64M1 22 ADC – Analog to Digital Converter ..................................................... 225 22.1 Features ........................................................................................................225 22.2 Operation .......................................................................................................227 22.3 Starting a Conversion ....................................................................................227 22.
ATmega16M1/32M1/64M1 27.1 Overview ........................................................................................................272 27.2 Application and Boot Loader Flash Sections .................................................272 27.3 Read-While-Write and No Read-While-Write Flash Sections ........................273 27.4 Boot Loader Lock Bits ...................................................................................275 27.5 Entering the Boot Loader Program ..................
ATmega16M1/32M1/64M1 33.1 Errata ATmega16M1 .....................................................................................329 33.2 Errata ATmega32M1 .....................................................................................329 33.3 Errata ATmega64M1 .....................................................................................329 34 Ordering Information ........................................................................... 330 34.1 ATmega16M1 ............................
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