Features • High Performance, Low Power AVR ® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory – 32K/64K Bytes Flash of In-System Programmable Program Memory • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits – In-Syste
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40°C to +125°C • Core Speed Grade: – 0 - 8MHz @ 2.7 - 4.5V – 0 - 16MHz @ 4.5 - 5.
ATmega32/64/M1/C1 1. Pin Configurations ATmega32/64M1 TQFP32/QFN32 (7*7 mm) Package. PD0 (PCINT16/PSCOUT0A) PC0(PCINT8/INT3/PSCOUT1A) PE0 (PCINT24/RESET/OCD) 32 31 30 29 28 27 26 25 PD1(PCINT17/PSCIN0/CLKO) ATmega32/64M1 TQFP32/QFN32 PB7 (ADC4/PSCOUT0B/SCK/PCINT7) PB6 (ADC7/PSCOUT1B/PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) Figure 1-1.
ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package PD0 (PCINT16) PC0(PCINT8/INT3) PE0 (PCINT24/RESET/OCD) 32 31 30 29 28 27 26 25 PD1(PCINT17/CLKO) ATmega32/64C1 TQFP32/QFN32 PB7 (ADC4/SCK/PCINT7) PB6 (ADC7PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) Figure 1-2.
ATmega32/64/M1/C1 1.1 Pin Descriptions : Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type 5 GND Power Ground: 0V reference 20 AGND Power Analog Ground: 0V reference for analog part 4 VCC Power Power Supply 19 AVCC Power Analog Power Supply: This is the power supply voltage for analog part Name, Function & Alternate Function For a normal use this pin must be connected. 21 AREF Power Analog Reference : reference for analog converter .
Table 1-1.
ATmega32/64/M1/C1 Table 1-1.
2.1 Block Diagram Figure 2-1. Block Diagram Data Bus 8-bit Flash Program Memory Program Counter Status and Control Interrupt Unit SPI Unit 32 x 8 General Purpose Registrers Instruction Register Direct Addressing Indirect Addressing 4 Analog Comparators Instruction Decoder Control Lines Watchdog Timer ALU HW LIN/UART Timer 0 Timer 1 Data SRAM ADC EEPROM DAC I/O Lines MPSC Current Source CAN The AVR core combines a rich instruction set with 32 general purpose working registers.
ATmega32/64/M1/C1 The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
2.3.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega32/64/M1/C1 The various special features of Port E are elaborated in “Alternate Functions of Port E” on page 77 and “Clock Systems and their Distribution” on page 29. 2.3.7 AVCC AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should be externally connected to VCC, even if the ADC, DAC are not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.8 AREF This is the analog reference pin for the A/D Converter. 2.
3. AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 Architectural Overview Figure 3-1.
ATmega32/64/M1/C1 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
3.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega32/64/M1/C1 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
Figure 3-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.
ATmega32/64/M1/C1 Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 3-4.
gramming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write SelfProgramming ATmega32/64M1” on page 272. 3.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
ATmega32/64/M1/C1 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 3.8.
4. Memories This section describes the different memories in the ATmega32/64/M1/C1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega32/64/M1/C1 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 4.1 In-System Reprogrammable Flash Program Memory The ATmega32/64/M1/C1 contains 32K/64K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega32/64/M1/C1 The ATmega32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 2304 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
Figure 3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 4.3 Next Instruction EEPROM Data Memory The ATmega32/64/M1/C1 contains 1024/2048 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
ATmega32/64/M1/C1 4.3.2 The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – - EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15.10 – Reserved Bits These bits are reserved bits in the ATmega32/64/M1/C1 and will always read as zero. • Bits 9..0 – EEAR8..
EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 4-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
ATmega32/64/M1/C1 When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
TABLE 1.
ATmega32/64/M1/C1 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. TABLE 2.
4.4 I/O Memory The I/O space definition of the ATmega32/64/M1/C1 is shown in “Register Summary” on page 346. All ATmega32/64/M1/C1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATmega32/64/M1/C1 5. System Clock 5.1 Clock Systems and their Distribution Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 39. The clock systems are detailed below. Figure 5-1.
5.1.4 PLL Clock – clkPLL The PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU. 5.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 5.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as illustrated Table 5-1.
ATmega32/64/M1/C1 frequency of the Watchdog Oscillator is voltage dependent as shown in “Watchdog Oscillator Frequency vs. VCC” on page 339. Table 5-2. 5.3 Number of Watchdog Oscillator Cycles Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536) Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed.
Table 5-3. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22 Notes: 1. The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5-4. Table 5-4. CKSEL0 SUT1..
ATmega32/64/M1/C1 ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 25-1 on page 312. By changing the OSCCAL register from SW, see “Oscillator Calibration Register – OSCCAL” on page 33, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in “Clock Characteristics” on page 312.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.
ATmega32/64/M1/C1 2. This value do not provide a proper restart ; do not use PD in this clock scheme 3. This value do not provide a proper restart ; do not use PD in this clock scheme Figure 5-3. PCK Clocking System OSCCAL PLLF PLLE PLOCK Lock Detector RC OSCILLATOR 8 MHz DIVIDE BY 8 PLL 64x CLK PLL DIVIDE BY 2 DIVIDE BY 4 CK SOURCE XTAL1 XTAL2 5.6.
Figure 5-4. External Clock Drive Configuration NC XTAL2 External Clock Signal XTAL1 GND Table 5-8. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-9. Table 5-9. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.
ATmega32/64/M1/C1 When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency.
the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 5-10.
ATmega32/64/M1/C1 6. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
6.2 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Transmit Complete interrupts.
ATmega32/64/M1/C1 with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Table 6-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Oscillator s clkADC clkPLL Main Clock Source Enabled INT3..
Writing a logic one to this bit reduces the consumption of the PSC by stopping the clock to this module. When waking up the PSC again, the PSC should be re initialized to ensure proper operation. • Bit 4 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit reduces the consumption of the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the setting of this bit.
ATmega32/64/M1/C1 nificantly to the total current consumption. Refer to “Brown-out Detection” on page 47 for details on how to configure the Brown-out Detector. 6.7.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power.
7. System Control and Reset 7.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega32/64/M1/C1 Figure 7-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 7-1. Symbol Reset Characteristics Parameter Power-on Reset Threshold Voltage (rising) VPOT Typ Max Units 1.1 1.4 1.7 V 0.8 0.9 1.6 V 0.4 V VPORMAX VCC Max.
Figure 7-2. MCU Start-up, RESET Tied to VCC V CCRR VCC VPORMAX VPORMIN RESET VRST tTOUT TIME-OUT INTERNAL RESET Figure 7-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 7.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 7-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega32/64/M1/C1 7.2.3 Brown-out Detection ATmega32/64/M1/C1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 7-2. BODLEVEL Fuse Coding(1)(2) BODLEVEL 2..
Figure 7-5. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET 7.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 50 for details on operation of the Watchdog Timer. Figure 7-6. Watchdog Reset During Operation CC CK 7.2.
ATmega32/64/M1/C1 This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program.
7.4 Watchdog Timer ATmega32/64/M1/C1 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 7-7.
ATmega32/64/M1/C1 The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR r16, (1<
ATmega32/64/M1/C1 • Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF.
. Table 7-6. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATmega32/64/M1/C1 8. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32/64/M1/C1. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 17. 8.1 Interrupt Vectors in ATmega32/64/M1/C1 Table 8-1. Reset and Interrupt Vectors Vector No.
Table 8-1. Reset and Interrupt Vectors Vector No. Program Address 29 Source Interrupt Definition 0x0038 WDT Watchdog Time-Out Interrupt 30 0x003A EE READY EEPROM Ready 31 0x003C SPM READY Store Program Memory Ready Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming ATmega32/64M1” on page 272. 2.
ATmega32/64/M1/C1 0x020 jmp TIM0_COMPB ; Timer0 Compare B Handler 0x022 jmp TIM0_OVF ; Timer0 Overflow Handler 0x024 jmp CAN_INT ; CAN MOB,Burst,General Errors Handler 0x026 jmp CAN_TOVF ; CAN Timer Overflow Handler 0x028 jmp LIN_TC ; LIN Transfer Complete Handler 0x02A jmp LIN_ERR ; LIN Error Handler 0x02C jmp PCINT0 ; Pin Change Int Request 0 Handler 0x02E jmp PCINT1 ; Pin Change Int Request 1 Handler 0x030 jmp PCINT2 ; Pin Change Int Request 2 Handler 0x032 jmp PCINT
0x03C jmp SPM_RDY ; Store Program Memory Ready Handler ; .
ATmega32/64/M1/C1 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles.
9. I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega32/64/M1/C1 9.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET 1 Q Pxn D 0 PORTxn Q CLR WPx DATA BUS RDx RESET WRx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK Note: 9.2.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 9.2.
ATmega32/64/M1/C1 Figure 9-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. TABLE 2. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16, (1<
ATmega32/64/M1/C1 9.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows how the port pin control signals from the simplified Figure 9-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 9-5.
Table 9-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega32/64/M1/C1 9.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 SPIPS – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Se 9.3.
ADC4, Analog to Digital Converter, input channel 4. SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. PCINT7, Pin Change Interrupt 7.
ATmega32/64/M1/C1 MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 and PUD bits. PSCOUT2A, Output 2A of PSC. PCINT0, Pin Change Interrupt 0.
Table 9-5. Overriding Signals for Alternate Functions in PB3..
ATmega32/64/M1/C1 9.3.3 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 9-6. Table 9-6.
ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT14, Pin Change Interrupt 14. • ADC9/ACMP3/AMP1+/PCINT13 – Bit 5 ADC9, Analog to Digital Converter, input channel 9. ACMP3, Analog Comparator 3 Positive Input.
ATmega32/64/M1/C1 PSCOUT1A, Output 1A of PSC. INT3, External Interrupt source 3: This pin can serve as an external interrupt source to the MCU. PCINT8, Pin Change Interrupt 8. Table 9-7 and Table 9-8 relate the alternate functions of Port C to the overriding signals shown in Figure 9-5 on page 65. Table 9-7. Overriding Signals for Alternate Functions in PC7..
9.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-9. Table 9-9.
ATmega32/64/M1/C1 ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT0, External Interrupt source 0. This pin can serve as an external interrupt source to the MCU. PCINT22, Pin Change Interrupt 23. • ADC2/ACMP2/PCINT21 – Bit 5 ADC2, Analog to Digital Converter, input channel 2. ACMP2, Analog Comparator 1 Positive Input.
MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDD2. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTD2 bit. PCINT18, Pin Change Interrupt 18. • PCINT17/PSCIN0/CLKO – Bit 1 PCSIN0, PSC Digital Input 0.
ATmega32/64/M1/C1 Table 9-11. Overriding Signals for Alternate Functions in PD3..
The alternate pin configuration is as follows: • PCINT26/XTAL2/ADC0 – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ADC0, Analog to Digital Converter, input channel 0. PCINT26, Pin Change Interrupt 26. • PCINT25/XTAL1/OC0B – Bit 1 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator.
ATmega32/64/M1/C1 9.4 9.4.1 Register Description for I/O-Ports Port B Data Register – PORTB Bit 9.4.2 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register – DDRB Bit 9.4.
9.4.9 Port D Input Pins Address – PIND Bit 9.4.
ATmega32/64/M1/C1 10. External Interrupts The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles.
10.2 External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 7..
ATmega32/64/M1/C1 10.2.2 External Interrupt Flag Register – EIFR Bit 7 6 5 4 3 2 1 0 – – – – INTF3 INTF2 INTF1 INTF0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIFR • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATmega32/64/M1/C1, and will always read as zero. • Bit 3..0 – INTF3 - INTF0: External Interrupt Flag 3 - 0 When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes set (one).
10.2.4 Pin Change Interrupt Flag Register - PCIFR Bit 7 6 5 4 3 2 1 0 – – – – PCIF3 PCIF2 PCIF1 PCIF0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCIFR • Bit 7..4 - Res: Reserved Bits These bits are unused bits in the ATmega32/64/M1/C1, and will always read as zero. • Bit 3 - PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT26..24 pin triggers an interrupt request, PCIF3 becomes set (one).
ATmega32/64/M1/C1 10.2.6 Pin Change Mask Register 2 – PCMSK2 Bit 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK2 • Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16 Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..
11. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 11.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega32/64/M1/C1 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selection is made thanks to ICPSEL1 bit as described in Table 11-1. Table 11-1. ICPSEL1 ICPSEL1 Description 0 Select ICP1A as trigger for timer 1 input capture 1 Select ICP1B as trigger for timer 1 input capture • Bit 0 – PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
ATmega32/64/M1/C1 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • • • • • • • 12.
The definitions in Table 12-1 are also used extensively throughout the document. Table 12-1. Definitions 12.1.2 BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.
ATmega32/64/M1/C1 count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
ATmega32/64/M1/C1 The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 12.
non-PWM modes refer to Table 12-2 on page 100. For fast PWM mode, refer to Table 12-3 on page 100, and for phase correct PWM refer to Table 12-4 on page 100. A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 12.6 Modes of Operation The mode of operation, i.e.
ATmega32/64/M1/C1 Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
ATmega32/64/M1/C1 12.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega32/64/M1/C1 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 12-10.
12.8 8-bit Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A Bit 7 6 5 4 3 2 1 0 COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
ATmega32/64/M1/C1 Table 12-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 Note: Description Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
Table 12-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 12-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 Note: Description Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. 1.
ATmega32/64/M1/C1 • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe.
12.8.3 Timer/Counter Register – TCNT0 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock.
ATmega32/64/M1/C1 overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. 12.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR0 Bit 7 6 5 4 3 2 1 0 – – – – – OCF0B OCF0A TOV0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega32/64/M1/C1 and will always read as zero.
13. 16-bit Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATmega32/64/M1/C1 Figure 13-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector Tn RTG TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB ICFn (Int.Req.) ICRn TCCRnA Note: 13.1.1 OCnB Edge Detector TCCRnB Noise Canceler AC1ICE ICPSEL1 0 1 ICPnA ICPnB Analog Comparator 1 Interrupt 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
ATmega32/64/M1/C1 Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle.
ATmega32/64/M1/C1 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle.
13.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega32/64/M1/C1 13.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 108. The ICF1 output can be used to retrigger the timer counter. It has the same effect than the TOP signal. 13.5.1 Input Capture Trigger Source The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change.
ATmega32/64/M1/C1 13.5.4 13.6 Using the Input Capture Unit as TCNT1 Retrigger Input TCNT1 counts from BOTTOM to TOP. The TOP value can be a fixed value, ICR1, or OCR1A. When enabled the Retrigger Input forces to reach the TOP value. It means that ICF1 output is ored with the TOP signal. Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match.
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly.
ATmega32/64/M1/C1 Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 13-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 13.8 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits.
ATmega32/64/M1/C1 Figure 13-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R FPWM = ---------------------------------log ( 2 ) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle.
ATmega32/64/M1/C1 Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 13-8. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs.
ATmega32/64/M1/C1 actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements.
Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
ATmega32/64/M1/C1 The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 13.
Figure 13-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx New OCRnx Value Old OCRnx Value (Update at TOP) Figure 13-13 shows the same timing data, but with the prescaler enabled. Figure 13-13.
ATmega32/64/M1/C1 I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 13-1 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 13-1.
Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/COMnB1 COMnA0/COMnB0 0 1 WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OCnA/OCnB on Compare Match when upcounting. Set OCnA/OCnB on Compare Match when downcounting. Set OCnA/OCnB on Compare Match when upcounting. Clear OCnA/OCnB on Compare Match when downcounting. 1.
ATmega32/64/M1/C1 Note: 13.10.2 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 13.10.
ATmega32/64/M1/C1 OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size.
13.10.7 Input Capture Register 1 – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
ATmega32/64/M1/C1 13.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1 Bit 7 6 5 4 3 2 1 0 – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega32/64/M1/C1, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
14. Power Stage Controller – (PSC) (only ATmega32/64M1) The Power Stage Controller is a high performance waveform controller. 14.
ATmega32/64/M1/C1 14.4 PSC Description Figure 14-1.
The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is able to count up to a top value determined by the contents of POCR_RB register and then according to the selected running mode, count down or reset to zero for another cycle. As can be seen from the block diagram Figure 14-1, the PSC is composed of 3 modules. Each of the 3 PSC modules can be seen as two symetrical entities.
ATmega32/64/M1/C1 Figure 14-3. Cycle Presentation in Centered Mode One PSC Cycle PSC Counter Value UPDATE Figure 14-2 and Figure 14-3 graphically illustrate the values held in the PSC counter. Centered Mode is like One Ramp Mode which counts down and then up. Notice that the update of the waveform generator registers is done regardless of ramp Mode at the end of the PSC cycle. 14.5.
Figure 14-4.
ATmega32/64/M1/C1 Figure 14-5. Controlled Start and Stop Mechanism in One-Ramp Mode POCRnRB POCRnSB POCRnRA POCRnSA PSC Counter 0 Run PSCOUTnA PSCOUTnB Note: 14.5.3.2 See “PSC Control Register – PCTL” on page 153. (PCCYC = 1) Center Aligned Mode In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered. Figure 14-6.
PSC Cycle = 2 * (POCRnRBH/L + 1) * 1/Fclkpsc Note: Minimal value for PSC Cycle = 2 * 1/Fclkpsc Note that in center aligned mode, POCRnRAH/L is not required (as it is in one-ramp mode) to control PSC Output waveform timing. This allows POCRnRAH/L to be freely used to adjust ADC synchronization (See “Analog Synchronization” on page 148.). Figure 14-7. Controlled Start and Stop Mechanism in Centered Mode POCRnRB POCRnSB POCRnSA PSC Counter 0 Run PSCOUTnA PSCOUTnB Note: 14.
ATmega32/64/M1/C1 14.6.1 Value Update Synchronization New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK configuration bit, the new whole set of values can be taken into account after the end of the PSC cycle. When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will be done at the end of the PSC cycle if the LOCK bit is released to zero.
14.8 Signal Description Figure 14-9. PSC External Block View CLK PLL CLK I/O POCRRB[11:0] POCR0SB[11:0] POCR0RA[11:0] POCR0SA[11:0] POCR1SB[11:0] POCR1RA[11:0] POCR1SA[11:0] POCR2SB[11:0] POCR2RA[11:0] POCR2SA[11:0] 12 PSCOUT0A 12 PSCOUT0B 12 PSCOUT1A PSCOUT1B 12 PSCOUT2A 12 PSCOUT2B 12 AC2O 12 AC1O 12 AC0O 12 PSCIN2 12 PSCIN1 PSCIN0 IRQ PSC 14.8.1 Input Description Table 14-1.
ATmega32/64/M1/C1 Name CLK I/O Clock Input from I/O clock Signal CLK PLL Clock Input from PLL Signal AC0O Analog Comparator 0 Output Signal AC1O Analog Comparator 1 Output Signal AC2O Analog Comparator 2 Output Signal Table 14-2. Name 14.8.2 Type Width Description Block Inputs Description Type Width PSCIN0 Input 0 used for Fault function Signal PSCIN1 Input 1 used for Fault function Signal PSCIN2 Input 2 used for Fault function Signal Output Description Table 14-3.
14.9 PSC Input For detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cookbook’, available on the Atmel web site. Each module 0, 1 and 2 of PSC has its own system to take into account one PSC input. According to PSC Module n Input Control Register (See “PSC Module n Input Control Register – PMICn” on page 154.), PSCINn input can act has a Retrigger or Fault input. Each block A or B is also configured by this PSC Module n Input Control Register (PMICn). Figure 14-10.
ATmega32/64/M1/C1 PSC Input Filterring CLKPSC Digital Filter 4 x CLK PSC PSC Input Module X 14.9.1.2 PSC Module n Input Ouput Stage PSCOUTnX PIN Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section "PSC Module n Input Control Register – PMICn", page 154.
Figure 14-11. PSC behaviour versus PSCn Input in Mode 001b to 10xb DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTnA PSCOUTnB PSCn Input Figure 14-12. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 PSCOUTnA PSCOUTnB PSCn Input PSCn Input acts indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action Figure 14-13.
ATmega32/64/M1/C1 Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
14.12 Analog Synchronization Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB outputs. In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchronization of the ADC. It this case, it’s minimum value is 1. 14.
ATmega32/64/M1/C1 Table 14-6. Output Clock versus Selection and Prescaler PCLKSELn PPREn1 PPREn0 CLKPSCn output 0 1 1 CLK I/O / 256 1 0 0 CLK PLL 1 0 1 CLK PLL / 4 1 1 0 CLK PLL / 32 1 1 1 CLK PLL / 256 14.15 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32/64/M1/C1. 14.15.1 Interrupt Vector PSC provides 2 interrupt vectors: 14.15.
• Bit 6 – not use not use • Bit 5 – POEN2B: PSC Output 2B Enable When this bit is clear, I/O pin affected to PSCOUT2B acts as a standard port. When this bit is set, I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveform generator B output and is set and clear according to the PSC operation. • Bit 4 – POEN2A: PSC Output 2A Enable When this bit is clear, I/O pin affected to PSCOUT2A acts as a standard port.
ATmega32/64/M1/C1 • Bit 5:4 – PSYNC21:0: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module 2 to the ADC for synchronization • Bit 3:2 – PSYNC11:0: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module 1 to the ADC for synchronization • Bit 1:0 – PSYNC01:0: Synchronization Out for ADC Selection Select the polarity and signal source for generating a sign
14.16.5 PSCOutput Compare SB Register – POCRnSBH and POCRnSBL Bit 7 6 5 4 – – – – 3 2 1 0 POCRnSB[11:8] POCRnSBH POCRnSB[7:0] 14.16.
ATmega32/64/M1/C1 • Bit 3 – POPB: PSC B Output Polarity If this bit is cleared, the PSC outputs B are active Low. If this bit is set, the PSC outputs B are active High. • Bit 2 – POPA: PSC A Output Polarity If this bit is cleared, the PSC outputs A are active Low. If this bit is set, the PSC outputs A are active High. • Bit 1:0 – not use not use 14.16.
14.16.9 PSC Module n Input Control Register – PMICn Bit 7 6 5 4 3 2 1 0 POVENn PISELn PELEVn PFLTEn PAOCn PRFMn2 PRFMn1 PRFMn0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PMICn The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. • Bit 7 – POVENn : PSC Module n Overlap Enable Set this bit to disactivate the Overlap Protection.
ATmega32/64/M1/C1 PRFMn2:0 Description 011b Disactivate module n Output A & B 10x Disactivate all PSC Output 11xb Halt PSC and Wait for Software Action 14.16.10 PSC Interrupt Mask Register – PIM Bit 7 6 5 4 3 2 1 0 - - - - PEVE2 PEVE1 PEVE0 PEOPE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PIM • Bit 7:4 – not use not use.
• Bit 2 – PEV1 : PSC External Event 1 Interrupt This bit is set by hardware when an external event which can generates a fault on module 1 occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVE1 bit = 0). • Bit 1 – PEV0 : PSC External Event 0 Interrupt This bit is set by hardware when an external event which can generates a fault on module 0 occurs. Must be cleared by software by writing a one to its location.
ATmega32/64/M1/C1 15. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32/64/M1/C1 and peripheral devices or between several AVR devices. The ATmega32/64/M1/C1 SPI includes the following features: 15.
the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start.
ATmega32/64/M1/C1 Table 15-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Alternate Functions of Port B” on page 67 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega32/64/M1/C1 Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<
15.2 15.2.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega32/64/M1/C1 15.2.4 SPI Control Register – SPCR Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled.
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clkIO frequency fclkio is shown in the following table: Table 15-4. 15.2.
ATmega32/64/M1/C1 15.2.6 SPI Data Register – SPDR Bit 7 6 5 4 3 2 1 0 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission.
Figure 15-4.
ATmega32/64/M1/C1 16. Controller Area Network - CAN The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The ATmega32/64/M1/C1 CAN controller is fully compatible with the CAN Specification 2.0 Part A and Part B.
by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automatically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. 16.2.2 16.2.2.1 Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier.
ATmega32/64/M1/C1 16.2.2.2 CAN Extended Frame Figure 16-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier IDT28..18 SOF SRR IDE 18-bit identifier extension ID17..0 RTR r1 Arbitration Field Interframe Space r0 4-bit DLC DLC4..0 15-bit CRC 0 - 8 bytes Control Field Data Field CRC Field CRC ACK del. ACK del. ACK Field 7 bits End of Frame Intermission Bus Idle 3 bits (Indefinite) Interframe Space Remote Frame Bus Idle 11-bit base identifier IDT28..
Figure 16-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point 16.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
ATmega32/64/M1/C1 The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT. 16.2.3.8 Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances.
Figure 16-4. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bus Node B wins the bus node B TXCAN CAN bus SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE 16.2.5 --------- Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: 16.2.5.
ATmega32/64/M1/C1 16.3 CAN Controller The CAN controller implemented into ATmega32/64/M1/C1 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored.
16.4 16.4.1 CAN Channel Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled, – the input clock is enabled. • Standby mode In standby mode: – the transmitter constantly provides a recessive level (on internal TxCAN) and the receiver is disabled, – input clock is enabled, – the registers and pages remain accessible.
ATmega32/64/M1/C1 The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 16-7. Sample and Transmission Point Bit Timing PRS (3-bit length) PHS1 (3-bit length) CLK Fcan (Tscl) Time Quantum Prescaler BRP IO Sample Point PHS2 (3-bit length) Transmission Point SJW (2-bit length) Figure 16-8. General Structure of a Bit Period 1 /CLK IO CLK IO Bit Rate Prescaler Tscl (TQ) F CAN one nominal bit Data Tsyns(5) Notes: 1. 2. 3. 4. 5.
5. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x Tscl Notes: 1. The total number of Tscl (Time Quanta) in a bit time must be from 8 to 25. 2. PHS2[2..0] 2 is programmable to be ≤ PHS1[2..0] and ≥ 1. 16.4.4 Fault Confinement (c.f. Section 16.7 “Error Management” on page 181). 16.4.5 Overload Frame An overload frame is sent by setting an overload request (OVRQ). After the next reception, the CAN channel sends an overload frame in accordance with the CAN specification.
ATmega32/64/M1/C1 16.5.2 Operating Modes There is no default mode after RESET. Every MOb has its own fields to control the operating mode. Before enabling the CAN peripheral, each MOb must be configured (ex: disabled mode - CONMOB=00). Table 16-1. MOb Configuration MOb Configuration 0 0 0 1 1 Reply Valid RTR Tag x x Disabled x 0 Tx Data Frame x 1 Tx Remote Frame x 0 Rx Data Frame 0 0 Operating Mode Rx Remote Frame 1 1 1 16.5.2.
2. The MOb is ready to receive a data or a remote frame when the MOb configuration is set (CONMOB). 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, tries to find the MOb having the highest priority which is matching. 4. On a hit, the IDT, the IDE and the DLC of the matched MOb are updated from the incoming (frame) values. 5.
ATmega32/64/M1/C1 16.5.3 Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and an IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT + RTRTAG + RBnTAG + IDE received are updated in the MOb (written over the registers). Figure 16-10.
The data index (INDX) is the address pointer to the required data byte. The data byte can be read or write. The data index is automatically incremented after every access if the AINC* bit is reset. A roll-over is implemented, after data index=7 it is data index=0. The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1, ... 16.6 CAN Timer A programmable 16-bit timer is used for message stamping and time trigger communication (TTC). Figure 16-11.
ATmega32/64/M1/C1 16.7 16.7.1 Error Management Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN macro detects an error. • Error passive: The CAN channel cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent.
– end-of-frame – error delimiter – overload delimiter • AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot. Figure 16-13. Error Detection Procedures in a Data Frame Arbitration Bit error Stuff error Form error Tx ACK error SOF Rx Identifier RTR Control Message Data CRC CRC ACK ACK del. del. EOF inter. Bit error Stuff error Form error CRC error 16.7.3 Error Setting The CAN channel can detect some errors on the CAN network.
ATmega32/64/M1/C1 Figure 16-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX CANSTMOB.6 TXOK[i] CANSTMOB.5 RXOK[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANSTMOB.2 CERR[i] CANSTMOB.1 FERR[i] CANSTMOB.0 AERR[i] ENRX ENERR CANSIT 1/2 SIT[i] CANIE 1/2 IEMOB[i] 0 CANGIT.7 i CANGIT.4 BXOK CANGIT.3 SERG CANGIT.2 CERG CANGIT.1 FERG CANGIT.0 AERG CANGIT.6 BOFFI CANGIT.5 OVRTIM CANIT CANGIE.2 CANGIE.1 CANGIE.6 CANGIE.
16.9 CAN Register Description Figure 16-15.
ATmega32/64/M1/C1 16.10 General CAN Registers 16.10.1 CAN General Control Register - CANGCON Bit 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CANGCON • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request. – 1 - abort request: a reset of CANEN1 and CANEN2 registers is done.
– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU.
ATmega32/64/M1/C1 • Bit 2 – ENFG: Enable Flag This flag does not generate an interrupt. – 0 - CAN controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode. – 1 - CAN controller enable. • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel. Only entering in bus off mode generates the BOFFIT interrupt. – 0 - no bus off mode. – 1 - bus off mode.
– 0 - no interrupt. – 1 - burst receive interrupt: set when the frame buffer receive is completed. • Bit 3 – SERG: Stuff Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. • Bit 2 – CERG: CRC Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - CRC error interrupt: the CRC check on destuffed message does not fit with the CRC field.
ATmega32/64/M1/C1 – 0 - interrupt disabled. – 1- transmit interrupt enabled. • Bit 3 – ENERR: Enable MOb Errors Interrupt – 0 - interrupt disabled. – 1- MOb errors interrupt enabled. • Bit 2 – ENBX: Enable Frame Buffer Interrupt – 0 - interrupt disabled. – 1- frame buffer interrupt enabled. • Bit 1 – ENERG: Enable General Errors Interrupt – 0 - interrupt disabled. – 1- general errors interrupt enabled. • Bit 0 – ENOVRT: Enable CAN Timer Overrun Interrupt – 0 - interrupt disabled.
16.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1 Bit 7 6 5 4 3 2 1 0 - - IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 CANIE2 - - - - - - - - CANIE1 Bit 15 14 13 12 11 10 9 8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 5:0 - IEMOB5:0: Interrupt Enable by MOb – 0 - interrupt disabled.
ATmega32/64/M1/C1 The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. BRP[5:0] + 1 Tscl = clkIO frequency If ‘BRP[5..0]=0’, see Section 16.4.3 “Baud Rate” on page 175 and Section • “Bit 0 – SMP: Sample Point(s)” on page 192. • Bit 0 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. 16.10.
• Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • Bit 6:4 – PHS22:0: Phase Segment 2 This phase is used to compensate for phase edge errors. This segment may be shortened by the re-synchronization jump width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f. Section 16.2.3 “CAN Bit Timing” on page 169 and Section 16.4.3 “Baud Rate” on page 175).
ATmega32/64/M1/C1 16.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH Bit 7 6 5 4 3 2 TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 1 0 TIMTTC1 TIMTTC0 CANTTCL TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 CANTTCH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 15:0 - TIMTTC15:0: TTC Timer Count CAN TTC timer counter range 0 to 65,535. 16.10.
• Bit 7:4 – MOBNB3:0: MOb Number Selection of the MOb number, the available numbers are from 0 to 5. Note: MOBNB3 always must be written to zero for compatibility with all AVR CAN devices. • Bit 3 – AINC: Auto Increment of the FIFO CAN Data Buffer Index (Active Low) – 0 - auto increment of the index (default value). – 1- no auto increment of the index. • Bit 2:0 – INDX2:0: FIFO CAN Data Buffer Index Byte location of the CAN data byte into the FIFO for the defined MOb. 16.
ATmega32/64/M1/C1 This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. • Bit 2 – CERR: CRC Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register.
– 0 - reply not ready. – 1 - reply ready and valid. • Bit 4 – IDE: Identifier Extension IDE bit of the remote or data frame to send. This bit is updated with the corresponding value of the remote or data frame received. – 0 - CAN standard rev 2.0 A (identifiers length = 11 bits). – 1 - CAN standard rev 2.0 B (identifiers length = 29 bits). • Bit 3:0 – DLC3:0: Data Length Code Number of Bytes in the data field of the message. DLC field of the remote or data frame to send. The range of DLC is from 0 up to 8.
ATmega32/64/M1/C1 These bits are reserved for future use. For compatibility with future devices, they must be written to zero when CANIDTn are written. When a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values. • Bit 2 – RTRTAG: Remote Transmission Request Tag RTR bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received.
Bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - V2.
ATmega32/64/M1/C1 – 0 - comparison true forced – 1 - bit comparison enabled. 16.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH Bit 7 6 5 4 3 2 1 0 TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 CANSTML TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 CANSTMH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value - - - - - - - - • Bits 15:0 - TIMSTM15:0: Time Stamp Count CAN time stamp counter range 0 to 65,535. 16.
Table 16-2. fCLKIO (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies CAN Rate (Kbps) 1000 Description Sampling Point 69 % (1) 75 % 500 75 % 250 75 % 200 75 % 125 75 % 100 75 % 1000 67 % (1) 500 75 % 250 75 % 200 75 % 125 75 % 100 75 % 16.000 12.000 200 Segments Registers TQ (µs) Tbit (TQ) Tprs (TQ) Tph1 (TQ) Tph2 (TQ) Tsjw (TQ) CANBT1 CANBT2 CANBT3 0.0625 16 7 4 4 1 0x00 0x0C 0x36 (2) 0.125 8 3 2 2 1 0x02 0x04 0x13 0.
ATmega32/64/M1/C1 Table 16-2. fCLKIO (MHz) Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) CAN Rate (Kbps) 1000 500 250 Description Sampling Point 63 % (1) TQ (µs) Segments Tbit (TQ) Note: data- - - 1 0x00 0x04 0x12 (2) 69 % (1) 0.125 16 7 4 4 1 0x00 0x0C 0x36 (2) 75 % 0.250 8 3 2 2 1 0x02 0x04 0x13 0.250 16 7 4 4 1 0x02 0x0C 0x37 75 % 75 % 100 75 % 0.500 8 3 2 2 1 0x06 0x04 0x13 0.250 20 8 6 5 1 0x02 0x0E 0x4B 0.
17. LIN / UART - Local Interconnect Network Controller or UART The LIN (Local Interconnect Network) is a serial communications protocol which efficiently supports the control of mechatronics nodes in distributed automotive applications.
ATmega32/64/M1/C1 17.3 17.3.1 LIN Protocol Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. Figure 17-1. LIN cluster with one master node and “n” slave nodes master node master task slave node 1 slave node n slave task slave task slave task LIN bus The master task decides when and which frame shall be transferred on the bus.
17.3.3 Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. • • Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always present at the same position in the data field for all frames with the same identifier. Diagnostic messages Diagnostic messages are transported in frames with two reserved identifiers.
ATmega32/64/M1/C1 forms to this perspective. The only link between the master task and the slave task will be at the cross-over point where the interrupt routine is called once a new identifier is available. Thus, in a master node, housing both master and slave task, the Tx LIN Header function will alert the slave task of an identifier presence. In the same way, in a slave node, the Rx LIN Header function will alert the slave task of an identifier presence.
17.4.3 LIN/UART Controller Structure Figure 17-4. LIN/UART Controller Block Diagram CLK IO RxD Finite State Machine Prescaler Sample /bit FSM BAUD_RATE Get Byte RX Put Byte TX Frame Time-out TxD Synchronization Monitoring Data FIFO 17.4.4 BUFFER LIN/UART Command Overview Figure 17-5.
ATmega32/64/M1/C1 Table 17-1. LIN/UART Command List LENA LCMD[2] LCMD[1] LCMD[0] Command 0 x x x Disable peripheral 0 Rx Header - LIN abort LIN withdrawal 1 Tx Header LCMD[2..0]=000 after Tx 0 Rx Response LCMD[2..0]=000 after Rx 1 Tx Response LCMD[2..0]=000 after Tx 0 0 Byte transfer 1 0 Rx Byte 0 1 Tx Byte 1 1 Full duplex 0 0 1 1 1 Comment no CRC, no Time out LTXDL=LRXDL=0 (LINDLR: read only register) 17.4.
17.4.6.2 Tx Header Function In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LINBTR registers). The controller is responsible for: • The transmission of the BREAK field - 13 dominant bits, • The transmission of the SYNCH field - character 0x55, • The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR register (automatic check bits included).
ATmega32/64/M1/C1 17.4.6.4 Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. “Data Management” on page 218). Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access. 17.4.7 UART Commands Setting the LCMD[2] bit in LINENR register enables UART commands.
17.5 17.5.1 LIN / UART Description Reset The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit performs a partial reset as shown in Table 17-2. Table 17-2. 17.5.2 Reset of LIN/UART Registers Register Name Reset Value LSWRES Value LIN Control Reg. LINCR 0000 0000 b 0000 0000 b LIN Status & Interrupt Reg. LINSIR 0000 0000 b 0000 0000 b LIN Enable Interrupt Reg.
ATmega32/64/M1/C1 The LIN configuration is independent of the programmed LIN protocol. The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same scheme is available in UART mode. Figure 17-6. Listening Mode internal Tx LIN TXLIN LISTEN 17.5.5 internal 1 Rx LIN 0 RXLIN Busy Signal LBUSY bit flag in LINSIR register is the image of the BUSY signal.
• “LIN Data Register” - LINDAT. The busy signal is not generated during a byte reception. 17.5.6 17.5.6.1 Bit Timing Baud rate Generator The baud rate is defined to be the transfer rate in bits per second (bps): • • • BAUD: Baud rate (in bps), fclki/o: System I/O clock frequency, LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives clki/o as input clock. • LBT[5..
ATmega32/64/M1/C1 Figure 17-8. Handling LBT[5..0] Write in LINBTR register =1 LENA ? (LINCR bit 4) =0 LDISR =1 to write =0 LBT[5..0] forced to 0x20 LDISR forced to 0 Enable re-synch. in LIN mode 17.5.7 LBT[5..0] = LBT[5..0] to write (LBT[5..0]min=8) LDISR forced to 1 Disable re-synch. in LIN mode Data Length Section 17.4.6 “LIN Commands” on page 207 describes how to set or how are automatically set the LRXDL[3..0] or LTXDL[3..
17.5.7.3 Data Length in Rx Response Figure 17-9. LIN2.1 - Rx Response - No error LIDOK LRXOK LIN bus LRXDL (*) 4 LTXDL (*) ? 1st Byte 2 nd Byte 3 rd Byte 4 th Byte DATA-0 DATA-1 DATA-2 DATA-3 CHECKSUM 1 2 3 4 0 LBUSY LCMD2..
ATmega32/64/M1/C1 17.5.7.5 Data Length after Error Figure 17-11. Tx Response - Error LERR LIN bus 1st Byte 2 nd Byte DATA-0 DATA-1 3 rd Byte DATA-2 ERROR LRXDL 4 LTXDL 4 0 1 2 LBUSY LCMD2..0=000b LCMD=Tx Response Note: 17.5.7.6 17.5.8 Information on response (ex: error on byte) is only available at the end of the serialization/de-serialization of the byte.
• • • • • ever, the LIN slave application has to solve this as: - known identifier (parity bits corrupted), - or corrupted identifier to be ignored, - or new identifier. LSERR = LIN Synchronization ERRor. A LIN synchronization error will be flagged if a slave detects the edges of the SYNCH field outside the given tolerance. LFERR = LIN Framing ERRor. A framing error will be flagged if dominant STOP bit is sampled. Same function in UART mode. LTOERR = LIN Time Out ERRor.
ATmega32/64/M1/C1 BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing of the new frame starts. • On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in case of Rx Response). Information on data error is also available, refer to the Section 17.5.7.5. • On master node, the user (code) is responsible for this aborting of frame.
Figure 17-13. LIN Interrupt Mapping LINERR.7 LABORT LINERR.6 LTOERR LINERR.5 LOVERR LINSIR.3 LINERR.4 LFERR LIN ERR LERR LINERR.3 LSERR LINENIR.3 LINENIR.2 LINENIR.1 LINENIR.0 LINERR.2 LPERR LENERR LINERR.1 LCERR LINSIR.2 LBERR LINSIR.1 LENIDOK LENTXOK LENRXOK LIDOK LINERR.0 LIN IT LTXOK LINSIR.0 LRXOK 17.5.14 Message Filtering Message filtering based upon the whole identifier is not implemented.
ATmega32/64/M1/C1 17.5.15.2 UART Data Register The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data out and in read access, LINDAT will be for data in. In UART mode the LINSEL register is unused. 17.5.16 OCD Support This chapter describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O view behavior in AVR Studio) 1. LINCR: - LINCR[6..
17.6 LIN / UART Register Description Table 17-5. LIN/UART Register Bits Summary Name LINCR LINSIR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSWRES LIN13 LCONF1 LCONF0 LENA LCMD2 LCMD1 LCMD0 0 R/W 0 0 LINBTR LINBRRL LINBRRH LINDLR LINIDR LINSEL LINDAT 17.6.
ATmega32/64/M1/C1 – 10 = No Frame_Time_Out (listen mode “off” & CRC “on”), – 11 = Listening mode (CRC “on” & Frame_Time_Out “on”). b. UART mode (default = 00): – 00 = 8-bit, no parity (listen mode “off”), – 01 = 8-bit, even parity (listen mode “off”), – 10 = 8-bit, odd parity (listen mode “off”), – 11 = Listening mode, 8-bit, no parity. • Bit 3 - LENA: Enable – 0 = Disable (both LIN and UART modes), – 1 = Enable (both LIN and UART modes). • Bit 2:0 - LCMD[2..
– 1 = An error has occurred. The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits. In UART mode, this bit is also cleared by reading LINDAT. • Bit 2 - LIDOK: Identifier Interrupt This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR. – 0 = No identifier, – 1 = Slave task: Identifier present, master task: Tx Header complete. The user clears this bit by writing 1, in order to reset this interrupt.
ATmega32/64/M1/C1 – 0 = Transmit performed interrupt masked, – 1 = Transmit performed interrupt enabled. • Bit 0 - LENRXOK: Enable Receive Performed Interrupt – 0 = Receive performed interrupt masked, – 1 = Receive performed interrupt enabled. 17.6.
– 1 = Checksum error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 0 - LBERR: Bit Error Flag – 0 = no error, – 1 = Bit error. This bit is cleared when LERR bit in LINSIR is cleared. 17.6.
ATmega32/64/M1/C1 In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max). In UART mode this field is unused. • Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max). In UART mode this field is unused. 17.6.
17.6.9 LIN Data Buffer Selection Register - LINSEL Bit 7 6 5 4 3 2 1 0 - - Read/Write - - - - LAINC LINDX2 LINDX1 LINDX0 - - R/W R/W R/W R/W Initial Value - - - - 0 0 0 0 LINSEL • Bits 7:4 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written.
ATmega32/64/M1/C1 18. Analog to Digital Converter - ADC 18.1 Features • • • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 8- 250 µs Conversion Time Up to 120 kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels 3 Differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40 Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
Figure 18-1. Analog to Digital Converter Block Schematic Current Source ISRCEN AREF / ISRC ISRC AREFEN AVCC Internal 2.
ATmega32/64/M1/C1 18.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity.
Figure 18-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLKADC ADATE ADIF SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega32/64/M1/C1 When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Changing Channel or Reference Selection” on page 232 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 3.
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 Next Conversion 8 11 12 13 14 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 18-7.
ATmega32/64/M1/C1 If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 25-3 on page 308. 18.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure the ADATE bit is reset. b.
ATmega32/64/M1/C1 Figure 18-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 18.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible.
18.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs using the AMPxIS bit with both inputs unconnected. (See “Amplifier 0 Control and Status register – AMP0CSR” on page 251., See “Amplifier 1 Control and Status register – AMP1CSR” on page 252.
ATmega32/64/M1/C1 Figure 18-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 18-12.
Figure 18-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 18.7 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATmega32/64/M1/C1 Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a reference voltage of VREF. Figure 18-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /Gain 0x3FF 0 VREF/Gain Differential Input Voltage (Volts) 0x200 Table 18-2. Correlation Between Input Voltage and Output Codes VADCn Read code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 0.999 VREF /GAIN 0x1FF 511 VADCm + 0.
– ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: 18.8 – ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. – ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
ATmega32/64/M1/C1 The measured voltage has a linear relationship to the temperature as described in Table 18-3 on page 241. The voltage sensitivity is approximately 1 mV/°C and the accuracy of the temperature measurement is +/- 10°C after bandgap calibration. Table 18-3. Temperature vs. Sensor Output Voltage (Typical Case) Temperature / °C -40 °C +25 °C +125 °C Voltage / mV 600 mV 762 mv 1012 mV The values described in Table 18-3 on page 241 are typical values.
Read/Write R/W R/W R/W - R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7, 6 – REFS1, 0: ADC Vref Selection Bits These 2 bits determine the voltage reference for the ADC. The different setting are shown in Table 18-4. Table 18-4.
ATmega32/64/M1/C1 • Bit 4, 2, 1, 0 – MUX4, MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits These 4 bits determine which analog inputs are connected to the ADC input. The different setting are shown in Table 18-5. Table 18-5.
• Bit 6– ADSC: ADC Start Conversion Bit Set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect. The first conversion performs the initialization of the ADC. • Bit 5 – ADATE: ADC Auto trigger Enable Bit Set this bit to enable the auto triggering mode of the ADC. Clear it to return in single conversion mode.
ATmega32/64/M1/C1 • Bit 6 – ISRCEN: Current Source Enable Set this bit to source a 100µA current to the AREF pin. Clear this bit to use AREF pin as Analog Reference pin. • Bit 5 – AREFEN: Analog Reference pin Enable Set this bit to connect the internal AREF circuit to the AREF pin. Clear this bit to disconnect the internal AREF circuit from the AREF pin. • Bit 4 – Res: Reserved Bit This bit is unused bit in the ATmega32/64/M1/C1, and will always read as zero.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read ADCH to have the conversion result. 18.9.4.1 ADLAR = 0 Bit Read/Write Initial Value 18.9.4.
ATmega32/64/M1/C1 analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 18.10 Amplifier The ATmega32/64/M1/C1 features three differential amplified channels with programmable 5, 10, 20, and 40 gain stage. Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a synchronization signal called in this document the amplifier synchronization clock.
Figure 18-16.
ATmega32/64/M1/C1 Figure 18-17. Amplifier synchronization timing diagram ADSC is set when the amplifier output is changing due to the amplifier clock switch Signal to be measured PSC Block PSCn_ASY AMPLI_clk (Sync Clock) CK ADC Valid sample ADSC ADC ADC Activity ADC Conv ADC Sampling ADC Sampling Aborted ADC Conv ADC Sampling ADCResult Ready ADCResult Ready In order to have a better understanding of the functioning of the amplifier synchronization, a timing diagram example is shown Figure 18-15.
Figure 18-18.
ATmega32/64/M1/C1 18.11 Amplifier Control Registers The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and AMP1CSR. Then the start of conversion is done via the ADC control and status registers. The conversion result is stored on ADCH and ADCL register which contain respectively the most significant bits and the less significant bits. 18.11.
In accordance with the Table 18-9, these 3 bits select the event which will generate the clock for the amplifier 0. This clock source is necessary to start the conversion on the amplified channel. Table 18-9. 18.11.
ATmega32/64/M1/C1 Set this bit to connect the amplifier 1 to the comparator 1 positive input. In this configuration the comparator clock is adapted to the amplifier clock and AMP1TS2,AMP1TS1, AMP1TS0 bits have no effect. Clear this bit to normally use the Amplifier 1. • Bit 2:0 – AMP1TS2,AMP1TS1, AMP1TS0: Amplifier 1 Clock Source Selection Bits In accordance with the Table 18-11, these 3 bits select the event which will generate the clock for the amplifier 1.
Table 18-12. Amplifier 2 Gain Selection AMP2G1 AMP2G0 Description 0 1 Gain 10 1 0 Gain 20 1 1 Gain 40 To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 Amplifier synchronization clock periods. • Bit 3 – AMPCMP2: Amplifier 2 - Comparator 2 connection Set this bit to connect the amplifier 2 to the comparator 2 positive input.
ATmega32/64/M1/C1 19. ISRC - Current Source 19.1 Features • 100µA Constant current source • ± 2% Absolute Accuracy The ATmega32/64/M1/C1 features a 100µA ±2% Current Source. After RESET or up on request, the current is flowing through an external resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using a resistor in serie with a ≤0.5% tolerance is recommended.
ATmega32/64/M1/C1 proposes to have an external resistor used in conjunction with the Current Source. The device measures the voltage to the boundaries of the resistance via the Analog to Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. In automotive applications, distributed voltages are very disturbed.
ATmega32/64/M1/C1 19.2.2 Voltage Reference for External Devices An external resistor used in conjunction with the Current Source can be used as voltage reference for external devices. Using a resistor in serie with a lower tolerance than the Current Source accuracy (≤2%) is recommended. Table 19-2 gives an example of voltage references using standard values of resistors. 19.2.
20. Analog Comparator The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx. 20.1 Features • • • • • 20.2 4 Analog Comparators High Speed Clocked Comparators +/-30mV Hysteresys 4 reference levels Generation of Configurable Interrupts Overview The ATmega32/64/M1/C1 features 4 fast analog comparators.
ATmega32/64/M1/C1 Figure 20-1.
20.4 Analog Comparator Register Description Each analog comparator has its own control register. A dedicated register has been designed to consign the outputs and the flags of the 4 analog comparators. 20.4.
ATmega32/64/M1/C1 Table 20-2. 20.4.
These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 20-4. Table 20-4. 20.4.3 Analog Comparator 1 negative input selection AC1M2 AC1M1 AC1M0 Description 0 0 0 “Vref”/6.40 0 0 1 “Vref”/3.20 0 1 0 “Vref”/2.13 0 1 1 “Vref”/1.60 1 0 0 Bandgap (1.
ATmega32/64/M1/C1 These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 20-6. Table 20-6. 20.4.4 Analog Comparator 2 negative input selection AC2M2 AC2M1 AC2M0 Description 0 0 0 “Vref”/6.40 0 0 1 “Vref”/3.20 0 1 0 “Vref”/2.13 0 1 1 “Vref”/1.60 1 0 0 Bandgap (1.
These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 20-6. Table 20-8. 20.4.5 Analog Comparator 3 negative input selection AC3M2 AC3M1 AC3M0 Description 0 0 0 “Vref”/6.40 0 0 1 “Vref”/3.20 0 1 0 “Vref”/2.13 0 1 1 “Vref”/1.60 1 0 0 Bandgap (1.
ATmega32/64/M1/C1 AC3O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. • Bit 2– AC2O: Analog Comparator 2 Output Bit AC2O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. • Bit 1– AC1O: Analog Comparator 1 Output Bit AC1O bit is directly the output of the Analog comparator 1.
21. Digital to Analog Converter - DAC 21.1 Features • • • • • 10 bits resolution 8 bits linearity +/- 0.5 LSB accuracy between 100mV and AVcc-100mV Vout = DAC*Vref/1023 The DAC could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver. • The output impedance of the driver is around 100 Ohms. So the driver is able to load a 1nF capacitance in parallel with a resistor higher than 33K with a time constant around 1us.
ATmega32/64/M1/C1 Figure 21-1. Digital to Analog Converter Block Schematic DAC Result D2A pin VRef DAC Output Driver 10 1 0 10 10 DAC High bits DAC Low bits Sources DACH Update DAC Trigger Edge Detector DAATE DACL DATS2 DATS1 DATS0 - DALA DAOE DAEN DACON 21.2 Operation The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value.
rupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 21.3.1 DAC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the DAC. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the DAC through a passive switch. The internal 2.
ATmega32/64/M1/C1 Table 1. DAC Auto Trigger source selection (Continued) DATS2 DATS1 DATS0 Description 1 0 0 Timer/Counter0 Overflow 1 0 1 Timer/Counter1 Compare Match B 1 1 0 Timer/Counter1 Overflow 1 1 1 Timer/Counter1 Capture Event • Bit 2 – DALA: Digital to Analog Left Adjust Set this bit to left adjust the DAC input data. Clear it to right adjust the DAC input data. The DALA bit affects the configuration of the DAC data registers.
To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate value, the DAC input values which are really converted into analog signal are buffered into unreachable registers. In normal mode, the update of the shadow register is done when the register DACH is written. In case DAATE bit is set, the DAC input values will be updated on the trigger event selected through DATS bits.
ATmega32/64/M1/C1 22. debugWIRE On-chip Debug System 22.1 Features • • • • • • • • • • 22.
22.4 • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
ATmega32/64/M1/C1 dent Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore.
Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. 23.3.
ATmega32/64/M1/C1 Figure 23-1. Read-While-Write vs.
Figure 23-2.
ATmega32/64/M1/C1 Table 23-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
23.5.1 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega32/64/M1/C1 clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles.
Figure 23-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 23.7 1. The different variables used in Figure 23-3 are listed in Table 23-9 on page 286. Self-Programming the Flash The program memory is updated in a page by page fashion.
ATmega32/64/M1/C1 23.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. 23.7.2 • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
23.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega32/64/M1/C1 value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 24-4 on page 290 for detailed description and mapping of the Extended Fuse byte. Bit 7 6 5 4 3 2 1 0 Rd – – – – EFB3 EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 23.7.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 23.7.12 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 23-6 shows the typical programming time for Flash accesses from the CPU. Table 23-6. 23.7.
ATmega32/64/M1/C1 ; re-enable the RWW section ldi spmcrval, (1<
23.7.14 ATmega32/64/M1/C1 - 32K -Flash Boot Loader Parameters In Table 23-7 through Table 23-9, the parameters used in the description of the self programming are given. Table 23-7.
ATmega32/64/M1/C1 See “Addressing the Flash During Self-Programming” on page 279 for details about the use of Zpointer during Self-Programming.
23.7.15 ATmega32/64/M1/C1 - 64K - Flash Boot Loader Parameters In Table 23-7 through Table 23-9, the parameters used in the description of the self programming are given. Table 23-10.
ATmega32/64/M1/C1 See “Addressing the Flash During Self-Programming” on page 279 for details about the use of Zpointer during Self-Programming. 24. Memory Programming 24.1 Program And Data Memory Lock Bits The ATmega32/64/M1/C1 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 24-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 24-1.
Table 24-3. Lock Bit Protection Modes(1)(2). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega32/64/M1/C1 Table 24-4. Extended Fuse Byte Extended Fuse Byte Description Default Value BODLEVEL2(1) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1(1) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(1) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 24.3 Bit No 1. See Table 7-2 on page 47 for BODLEVEL Fuse decoding.
Table 24-6.
ATmega32/64/M1/C1 the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 24.4 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. 24.4.1 Signature Bytes For the ATmega32M1 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel). 2.
Figure 24-1. Parallel Programming + 5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 VCC XA1 PAGEL + 12 V + 5V AVCC PB[7:0] PD6 DATA PD7 RESET BS2 PE2 XTAL1 GND Table 24-8.
ATmega32/64/M1/C1 Table 24-10. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 24-11.
24.7 Serial Programming Pin Mapping Table 24-14. Pin Mapping Serial Programming 24.8 24.8.1 Symbol Pins I/O Description MOSI_A PD3 I Serial Data in MISO_A PD2 O Serial Data out SCK_A PD4 I Serial Clock Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) > Programming mode: 1. Set Prog_enable pins listed in Table 24-9. to “0000”, RESET pin to “0” and Vcc to 0V. 2. Apply 4.5 - 5.5V between VCC and GND.
ATmega32/64/M1/C1 changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6.
eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Give WR a negative pulse.
ATmega32/64/M1/C1 Figure 24-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 24.8.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 24-13 on page 295.
Figure 24-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 24.8.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 297 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4.
ATmega32/64/M1/C1 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 24.8.10 Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the Flash” on page 297 for details on Command and Data loading): 1. 1.
1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). 5. Set OE to “0”, BS2 to “0” and BS1 to “1”.
ATmega32/64/M1/C1 24.8.15 Parallel Programming Characteristics Figure 24-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 24-8.
Figure 24-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 24-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 24-15.
ATmega32/64/M1/C1 Table 24-15. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min tBVDV BS1 Valid to DATA valid tOLDV OE Low to DATA Valid 0 Typ Max Units 250 ns 250 ns tOHDZ Notes: 1. OE High to DATA Tri-stated 250 ns tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 24.
When reading data from the ATmega32/64/M1/C1, data is clocked on the falling edge of SCK. See Figure 24-11 for timing details. To program and verify the ATmega32/64/M1/C1 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 24-17): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up.
ATmega32/64/M1/C1 a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device.
Table 24-17. Serial Programming Instruction Set (Continued) Instruction Format Instruction Load EEPROM Memory Page (page access) Write EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Byte4 1100 0001 0000 0000 0000 00bb iiii iiii 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 24-1 on page 289 for details. 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits.
ATmega32/64/M1/C1 25. Electrical Characteristics All DC/AC characteristics contained in this datasheet are based on simulations and characterization of similar devices in the same process and design methods. These values are preliminary representing design targets, and will be updated after characterization of actual automotive silicon data. 25.1 Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +125°C Storage Temperature .....................................
25.2 DC Characteristics TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIH Input High Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIL1 Input Low Voltage VIH1 Max. Units -0.5 0.2VCC(1) V 0.6VCC(2) VCC+0.5 V XTAL1 pin , External Clock Selected -0.5 0.1VCC(1) V Input High Voltage XTAL1 pin , External Clock Selected 0.7VCC(2) VCC+0.
ATmega32/64/M1/C1 TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 8 MHz, VCC = 3V, RC osc, PRR = 0xFF 3.8 mA Active 16 MHz, VCC = 5V, Ext Clock, PRR = 0xFF 14 mA Idle 8 MHz, VCC = 3V, RC Osc 1.5 mA Idle 16 MHz, VCC = 5V, Ext Clock 5.
25.3 25.3.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 25-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±1% User Calibration 7.3 - 8.1 MHz 2.7V - 5.5V -40°C - 125°C ±10% 25.4 External Clock Drive Characteristics Figure 25-1. External Clock Drive Waveforms V IH1 V IL1 Table 2. External Clock Drive 25.5 VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max.
ATmega32/64/M1/C1 Figure 25-2. Maximum Frequency vs. VCC, ATmega32/64/M1/C1 16Mhz 8Mhz Safe Operating Area 2.7V 25.6 4.5V 5.5V PLL Characteristics . Table 3. PLL Characteristics - VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Min. Typ. Max. Units PLLIF Input Frequency 0.
25.7 SPI Timing Characteristics See Figure 25-3 and Figure 25-4 for details. Table 4. SPI Timing Parameters Description Mode 1 SCK period Master See Table 15-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega32/64/M1/C1 Figure 25-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
25.8 ADC Characteristics Table 25-2. Symbol ADC Characteristics - TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 2.56V ADC clock = 500 kHz 2.5 LSB Single Ended Conversion VREF = 2.56V ADC clock = 1MHz 6 LSB Resolution Absolute accuracy Single Ended Conversion VREF = 2.56V ADC clock = 2MHz LSB Differential Conversion VREF = 2.
ATmega32/64/M1/C1 Table 25-2. Symbol ADC Characteristics - TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Parameter Condition Min Typ Max Units Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -4 0 LSB Single Ended Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -2 2.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 1MHz -0.5 0.5 LSB Differential Conversion VCC = 4.5V, VREF = 4V ADC clock = 500 kHz -0.5 0.
25.9 Parallel Programming Characteristics Figure 25-5. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 25-6.
ATmega32/64/M1/C1 Figure 25-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) ADDR1 (Low Byte) DATA (High Byte) XA0 XA1 Note: 1. ggThe timing requirements shown in Figure 25-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 25-3.
Table 25-3. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min. tXLOL XTAL1 Low to OE Low 0 tBVDV BS1 Valid to DATA valid 0 tOLDV OE Low to DATA Valid Typ. Max. Units ns 250 ns 250 ns OE High to DATA Tri-stated 250 ns tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. tOHDZ Notes: 1. 26.
ATmega32/64/M1/C1 26.1 Active Supply Current Figure 26-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY ICC (mA) 1.6 1.4 5.5 V 1.2 5.0 V 4.5 V 4.0 V 1 0.8 3.3 V 3.0 V 2.7 V 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 Frequency (MHz) Figure 26-2. Active Supply Current vs. Frequency (1 - 24 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 30 25 5.5 V 5.0 V 20 ICC (mA) 4.5 V 15 4.0 V 10 3.3 V 3.0 V 5 2.
Figure 26-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 105 °C 85 °C 25 °C -40 °C 9 8 7 ICC (mA) 6 5 4 3 2 1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-4. Active Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz) ACTIVE SUPPLY CURRENT vs.
ATmega32/64/M1/C1 26.2 Idle Supply Current Figure 26-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0,45 0,4 5.5 V ICC (mA) 0,35 5.0 V 0,3 4.5 V 0,25 4.0 V 0,2 3.3 V 3.0 V 2.7 V 0,15 0,1 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 26-6. Idle Supply Current vs. Frequency (1 - 24 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 12 10 5.5 V 5.0 V 8 ICC (mA) 4.5 V 6 4.0 V 4 3.3 V 3.0 V 2 2.
Figure 26-7. IIdle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 4 3,5 105 °C 85 °C 25 °C -40 °C 3 ICC (mA) 2,5 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-8. Idle Supply Current vs. VCC (Internal PLL Oscillator, 16 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL PLL OSCILLATOR, 16 MHz 9 105 °C 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) 26.2.
ATmega32/64/M1/C1 are controlled by the Power Reduction Register. See “Power Reduction Register” on page 41 for details. Table 26-1. PRR bit Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 3V, F = 8MHz VCC = 5V, F = 16MHz PRCAN PRPSC PRTIM1 PRTIM0 PRSPI PRLIN PRADC Table 26-2.
26.3 Power-Down Supply Current Figure 26-9. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 7 105 °C 6 ICC (uA) 5 4 3 85 °C 2 -40 °C 25 °C 1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-10. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
ATmega32/64/M1/C1 26.4 Standby Supply Current Figure 26-11. Standby Supply Current vs. VCC (Crystal Oscillator) STANDBY SUPPLY CURRENT vs. VCC Full Swing Crystal Oscillator 500 450 TE LA ER P T M AC TE R HA C BE O T 400 ICC (uA) 350 300 250 200 150 16 MHz Xtal D IZE 12 MHz Xtal 6 MHz Xtal (ckopt) 4 MHz Xtal (ckopt) 2 MHz Xtal (ckopt) 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 26.5 Pin Pull-up Figure 26-12. I/O Pin Pull-Up Resistor Current vs.
Figure 26-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7 V -40 °C 90 25 °C 80 85 °C 105 °C 70 60 IOP (uA) 50 40 30 20 10 0 -10 0 0,5 1 1,5 2 2,5 3 V OP (V) Figure 26-14. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.
ATmega32/64/M1/C1 Figure 26-15. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) PE0 and RESET PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7 V 70 25 °C -40 °C 60 85 °C 105 °C 50 IOP (uA) 40 30 20 10 0 0 0,5 1 1,5 2 2,5 3 V OP (V) 26.6 Pin Driver Strength Figure 26-16. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5.
Figure 26-17. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7 V 25 105 °C 85 °C IOH (mA) 20 25 °C -40 °C 15 10 5 0 0 0,5 1 1,5 2 2,5 3 V OH (V) Figure 26-18. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5.
ATmega32/64/M1/C1 Figure 26-19. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN (including PE1 & PE2) SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7 V 25 -40 °C 25 °C 85 °C 105 °C 20 IOL (mA) 15 10 5 0 0 0,5 1 1,5 2 2,5 3 -5 V OL (V) 26.7 Pin Thresholds and Hysteresis Figure 26-20. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs.
Figure 26-21. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') I/O PIN (including PE1 & PE2) INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2,5 Threshold (V) 2 -40 °C 25 °C 85 °C 105 °C 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-22. I/O Pin Input HysteresisVoltage vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40 C 0.5 25 C Input Hysteresis ( V) 0.4 85 C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega32/64/M1/C1 Figure 26-23. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2,5 Threshold (V) 2 -40 °C 25 °C 85 °C 105 °C 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-24. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') RESET INPUT THRESHOLD VOLTAGE vs.
Figure 26-25. Reset Input Pin Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0,6 -40 °C Input Hysteresis (V) 0,5 0,4 25 °C 0,3 0,2 85 °C 105 °C 0,1 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-26. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '1') XTAL1 INPUT THRESHOLD VOLTAGE vs.
ATmega32/64/M1/C1 Figure 26-27. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '0') XTAL1 INPUT THRESHOLD VOLTAGE vs. VCC XTAL1 PIN READ AS "0" 4 3,5 Threshold (V) 3 2,5 -40 °C 25 °C 85 °C 105 °C 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-28. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '1') PE0 INPUT THRESHOLD VOLTAGE vs.
Figure 26-29. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '0') PE0 INPUT THRESHOLD VOLTAGE vs. VCC VIL, PE0 PIN READ AS '0' 2,5 105 °C 85 °C 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) 26.8 BOD Thresholds and Analog Comparator Hysterisis Figure 26-30. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 4.
ATmega32/64/M1/C1 Figure 26-31. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLV IS 2.7 V 2,82 2,8 Rising Vcc Threshold (V) 2,78 2,76 2,74 Falling Vcc 2,72 2,7 2,68 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) Figure 26-32. TypicalAnalog Comparator Hysterisis Average Thresholds vs. Common Mode Voltage 40.00E-3 30.00E-3 20.00E-3 threshold value (V) 10.00E-3 000.00E+0 0.5 1 1.35 1.5 2 2.5 2.6 2.
26.9 Analog Reference Figure 26-33. AREF Voltage vs. VCC AREF VOLTAGE vs. VCC 2,6 105 °C 85 °C 25 °C 2,55 -40 °C Aref (V) 2,5 2,45 2,4 2,35 2,3 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 26-34. AREF Voltage vs. Temperature AREF VOLTAGE vs. TEMPERATURE 2.59 2.58 5.5 5 4.5 3 Aref (V) 2.57 2.56 2.55 2.54 2.53 2.
ATmega32/64/M1/C1 26.10 Internal Oscillator Speed Figure 26-35. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 108 106 FRC (kHz) -40 °C 104 25 °C 102 100 85 °C 98 105 °C 96 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.4 8.3 TE 8.2 LA P TE M C TE RA A CH E B TO FRC (MHz) 8.1 8 7.9 7.8 7.7 ZE RI D 5.0 V 2.7 V 1.8 V 7.
Figure 26-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 8.6 8.4 TE IZE A R PL TE M C TE RA A H C BE O T FRC (MHz) 8.2 8 7.8 D 85 ˚C 25 ˚C -40 ˚C 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 26-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs.
ATmega32/64/M1/C1 26.11 Current Consumption of Peripheral Units Figure 26-39. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 45 40 35 ICC (uA) 30 105 °C 85 °C 25 °C -40 °C 25 20 15 10 5 0 2 2,5 3 3,5 4 4,5 5 5,5 V CC (V) Figure 26-40. ADC Current vs. VCC (ADC at 50 kHz) AREF vs. VCC ADC AT 50 KHz 500 450 -40 °C ICC (uA) 400 350 TE 300 250 TO 200 L MP BE E AT AR H C A CT ZE I ER D 25 °C 85 °C 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 26-41. Aref Current vs. VCC (ADC at 1 MHz) AREF vs. VCC ADC AT 1 MHz 180 85 ˚C 25 ˚C -40 ˚C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 26-42. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs.
ATmega32/64/M1/C1 Figure 26-43. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 14 -40 ˚C 12 ICC (mA) 10 25 ˚C 8 85 ˚C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 26.12 Current Consumption in Reset and Reset Pulse width Figure 26-44. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP ICC (mA) 0,18 0,16 5.5 V 0,14 5.0 V 0,12 4.5 V 0,1 4.0 V 0,08 3.3 V 3.0 V 2.
Figure 26-45. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 4 5.5 V 3,5 5.0 V 3 4.5 V ICC (mA) 2,5 2 4.0 V 1,5 3.3 V 1 3.0 V 2.7 V 0,5 0 0 5 10 15 20 25 Frequency (MHz) Figure 26-46. Reset Supply Current vs. VCC (Clock Stopped, Excluding Current through the Reset Pull-up) RESET CURRENT vs.
ATmega32/64/M1/C1 Figure 26-47. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs.
27.
ATmega32/64/M1/C1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved – – – – – – – – Page (0xBD) Reserved – – – – – – – – (0xBC)(5) PIFR – – – – PEV2 PEV1 PEV0 PEOP page 155 (0xBB)(5) PIM – – – – PEVE2 PEVE1 PEVE0 PEOPE page 155 (0xBA)(5) PMIC2 POVEN2 PISEL2 PELEV2 PFLTE2 PAOC2 PRFM22 PRFM21 PRFM20 page 154 (0xB9)(5) PMIC1 POVEN1 PISEL1 PELEV1 PFLTE1 PAOC1 PRFM12 PRFM11 PRFM10 page 154 (0xB8)(5) PMIC0 POVE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 241 (0x7B) ADCSRB ADHSM ISRCEN AREFEN – ADTS3 ADTS2 ADTS1 ADTS0 page 244 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 243 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 245 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 / - ADC0
ATmega32/64/M1/C1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 28 0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 28 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) Reserved – – – – – – – – 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 133 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TO
28.
ATmega32/64/M1/C1 Mnemonics Operands Description Operation Flags BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None #Clocks 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd R
Mnemonics Operands Description Operation Flags #Clocks POP Rd Pop Register from Stack Rd ← STACK None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: 352 1.
ATmega32/64/M1/C1 29. Errata 29.1 29.1.1 Errata Summary ATmega32/64/M1/C1 Rev. A (Mask Revision) • Inopportune reset of the CANIDM registers. 29.2 Errata Description 1. Inopportune reset of the CANIDM registers After the reception of a CAN frame in a MOb, the ID mask registers are reset. Problem fix / workaround Before enabling a MOb in reception, re-initialize the ID mask registers - CANIDM[4..1].
30. Ordering Information Figure 30-1. ATmega32M1 engineering samples delivery only. Automotive qualification not yet fully completed. Memory Size Note: Power Supply Ordering Code Package 32K 2.7 - 5.5V AT90PWM324-ESAZ MA (TQFP32) 32K 2.7 - 5.5V AT90PWM324-ESMZ PN (QFN32) 32K 2.7 - 5.5V AT90CAN321-ESAZ MA (TQFP32) 32K 2.7 - 5.
ATmega32/64/M1/C1 31. Package Information Package Type MA MA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) PV PV, 32-Lead, 5.0x5.0 mm Body, 0.
31.
ATmega32/64/M1/C1 31.
32. Datasheet Revision History for ATmega32/64/M1/C1 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 32.1 7647A 1. First document revision.
ATmega32/64/M1/C1 Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 3 1.1 2 3 4 5 Pin Descriptions .................................................................................................5 Overview ................................................................................................... 7 2.1 Block Diagram .........
6 7 8 Power Management and Sleep Modes ................................................. 39 6.1 Sleep Mode Control Register ..........................................................................39 6.2 Idle Mode .........................................................................................................40 6.3 ADC Noise Reduction Mode ............................................................................40 6.4 Power-down Mode ...................................................
ATmega32/64/M1/C1 12.7 Timer/Counter Timing Diagrams .....................................................................98 12.8 8-bit Timer/Counter Register Description ......................................................100 13 16-bit Timer/Counter1 with PWM ........................................................ 106 13.1 Overview ........................................................................................................106 13.2 Accessing 16-bit Registers ...........................
16 Controller Area Network - CAN ........................................................... 167 16.1 Features ........................................................................................................167 16.2 CAN Protocol .................................................................................................167 16.3 CAN Controller ..............................................................................................173 16.4 CAN Channel ................................
ATmega32/64/M1/C1 19.3 Control Register .............................................................................................257 20 Analog Comparator ............................................................................. 258 20.1 Features ........................................................................................................258 20.2 Overview ........................................................................................................258 20.
24.8 Parallel Programming ....................................................................................296 24.9 Serial Downloading ........................................................................................305 25 Electrical Characteristics(1) ................................................................................................ 309 25.1 Absolute Maximum Ratings* .........................................................................309 25.2 DC Characteristics .......
ATmega32/64/M1/C1 32 Datasheet Revision History for ATmega32/64M1 ............................. 358 32.1 7647A ............................................................................................................
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