Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16K bytes of In-System Self-Programmable Flash Endurance: 1,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Program
LCDCAP 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 1.
ATmega169V/L Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram PA0 - PA7 XTAL1 PF0 - PF7 XTAL2 Figure 2. Block Diagram PC0 - PC7 VCC GND PORTA DRIVERS PORTF DRIVERS DATA DIR. REG.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega169V/L Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). PG5 is input only, the rest of the pins are bi-directional.
ATmega169V/L AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
ATmega169V/L Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega169V/L The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega169V/L moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 251. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega169V/L AVR ATmega169 Memories This section describes the different memories in the ATmega169. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega169 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 9 shows how the ATmega169 SRAM Memory is organized. The ATmega169 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 1,280 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
ATmega169V/L Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction EEPROM Data Memory Next Instruction The ATmega169 contains 512 bytes of data EEPROM memory.
The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bits 8..0 – EEAR8..
ATmega169V/L • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega169V/L The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
I/O Memory The I/O space definition of the ATmega169 is shown in “Register Summary” on page 302. All ATmega169 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATmega169V/L System Clock and Clock Options Clock Systems and their Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed below. Figure 11.
ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 2.
ATmega169V/L Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage (1) 14CK + 4.1 ms Ceramic resonator, fast rising power 0 00 258 CK 0 01 258 CK (1) 14CK + 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14CK + 4.
ATmega169V/L Table 7. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save CKSEL3..0 0100 Recommended Usage 1K CK 0101 32K CK 0110(1) 1K CK 0111 32K CK Note: Calibrated Internal RC Oscillator (1) Stable frequency at start-up Stable frequency at start-up 1. These options should only be used if frequency stability at start-up is not important for the application The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock.
Oscillator Calibration Register – OSCCAL Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R R/W R/W R/W R/W R/W R/W R/W OSCCAL Device Specific Calibration Value • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset.
ATmega169V/L External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 13. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 11. Crystal Oscillator Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz Table 12.
Timer/Counter Oscillator ATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized for use with a 32.768 kHz watch crystal. See Figure 12 on page 25 for crystal connection. Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one.
ATmega169V/L frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 13.
Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
ATmega169V/L Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep.
ATmega169V/L Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 39 for details on how to configure the Brown-out Detector.
System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega169V/L Figure 14. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 16.
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 16. The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATmega169V/L External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 16) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 17.
When the BOD is enabled, and V CC decreases to a value below the trigger level (VBOTin Figure 18), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 18), the delay counter starts the MCU after the Timeout period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 16. Figure 18.
ATmega169V/L • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 21 on page 43. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
ATmega169V/L Watchdog Timer Control Register – WDTCR Bit 7 6 5 4 3 2 1 0 – – – WDCE WDE WDP2 WDP1 WDP0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WDTCR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega169V/L Interrupts Interrupt Vectors in ATmega169 This section describes the specifics of the interrupt handling as performed in ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 22. Reset and Interrupt Vectors Vector No.
Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 23.
ATmega169V/L When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code 0x0000 RESET: ldi Comments 0x0001 out SPH,r16 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out sei SPL,r16 0x0005 r16,high(RAMEND) ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts x
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x1C00 0x1C00 0x1C02 jmp jmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler 0x1C04 jmp PCINT0 ; PCINT0 Handler ... ... ...
ATmega169V/L • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega169V/L Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 22.
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
ATmega169V/L Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega169V/L Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 25.
Table 25. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega169V/L MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 51 for more details about this feature.
Table 28. Overriding Signals for Alternate Functions in PA3..
ATmega169V/L • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.
• SCK/PCINT9 – Port B, Bit 1 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source.
ATmega169V/L Table 31. Overriding Signals for Alternate Functions in PB3..
Table 33 and Table 34 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 55. Table 33. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/SEG5 PC6/SEG6 PC5/SEG7 PC4/SEG8 PUOE LCDEN LCDEN LCDEN LCDEN PUOV 0 0 0 0 DDOE LCDEN LCDEN LCDEN LCDEN DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE LCDEN LCDEN LCDEN LCDEN DIEOV 0 0 0 0 DI – – – – AIO SEG5 SEG6 SEG7 SEG8 Table 34.
ATmega169V/L Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 35. Table 35.
Table 36 and Table 37 relates the alternate functions of Port D to the overriding signals shown in Figure 25 on page 55. Table 36. Overriding Signals for Alternate Functions PD7..
ATmega169V/L Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 38. Table 38.
• XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source. • TXD/PCINT1 – Port E, Bit 1 TXD0, UART0 Transmit pin.
ATmega169V/L Table 40. Overriding Signals for Alternate Functions in PE3..
• TCK, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5. TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
ATmega169V/L Table 43. Overriding Signals for Alternate Functions in PF3..PF0 Alternate Functions of Port G Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT The alternate pin configuration is as follows: Table 44.
• SEG4 – Port G, Bit 2 SEG4, LCD front plane 4 • SEG13 – Port G, Bit 1 SEG13, Segment driver 13 • SEG14 – Port G, Bit 0 SEG14, LCD front plane 14 Table 44 and Table 45 relates the alternate functions of Port G to the overriding signals shown in Figure 25 on page 55. Table 45.
ATmega169V/L Table 46.
Register Description for I/O-Ports Port A Data Register – PORTA Bit Port A Data Direction Register – DDRA Port A Input Pins Address – PINA 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2
ATmega169V/L Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINC Port D Data Register – PORTD Bit Port D Data Direction Register – DDRD Port D Input Pins Address – PIND 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0
Port F Input Pins Address – PINF Bit 7 6 5 4 3 2 1 0 PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINF Port G Data Register – PORTG Bit Port G Data Direction Register – DDRG Port G Input Pins Address – PING 74 7 6 5 4 3 2 1 0 – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6
ATmega169V/L External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 PCIE1 PCIE0 – – – – – INT0 Read/Write R/W R/W R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bit 7 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt.
ATmega169V/L • Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.
8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26.
ATmega169V/L event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit channel, in this case channel A. However, when using the register or bit defines in a program, the precise form must be used, i.e.
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
ATmega169V/L The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
Compare Match Output Unit The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 29 shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega169V/L Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1).
ATmega169V/L The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 51 on page 89).
Figure 32. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATmega169V/L Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 33 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 33.
Figure 36 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 36.
ATmega169V/L Table 49. Waveform Generation Mode Bit Description(1) Mode WGM01 (CTC0) WGM00 (PWM0) Timer/Counter Mode of Operation TOP Update of OCR0A at TOV0 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0A Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Table 52. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 Reserved 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when downcounting. 1 1 Set OC0A on compare match when up-counting. Clear OC0A on compare match when downcounting. Note: Description 1.
ATmega169V/L Output Compare Register A – OCR0A Bit 7 6 5 4 3 2 1 0 OCR0A[7:0] OCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.
Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega169V/L the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 38.
16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATmega169V/L Figure 39. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 188.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
ATmega169V/L Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega169V/L The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 92. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
ATmega169V/L how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 106. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 97.
ATmega169V/L Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed.
(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first.
ATmega169V/L Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 43 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 55 on page 116. For fast PWM mode refer to Table 56 on page 116, and for phase correct and phase and frequency correct PWM refer to Table 57 on page 117.
ATmega169V/L Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP.
ATmega169V/L When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value.
Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega169V/L ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers.
Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATmega169V/L The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 48 shows a timing diagram for the setting of OCF1x. Figure 48.
ATmega169V/L Figure 50. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 51 shows the same timing data, but with the prescaler enabled. Figure 51.
16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATmega169V/L Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 57. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when upcounting.
Table 58.
ATmega169V/L (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.
ATmega169V/L Input Capture Register 1 – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
Timer/Counter1 Interrupt Flag Register – TIFR1 Bit 7 6 5 4 3 2 1 0 – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.
ATmega169V/L 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC2A). See “Output Compare Unit” on page 125. for details.
ATmega169V/L top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped.
The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega169V/L Compare Match Output Unit The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 55 shows a simplified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega169V/L compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 63 on page 135).
ATmega169V/L Figure 58. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are set. Figure 59 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 59.
ATmega169V/L Figure 61. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 62 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 62.
8-bit Timer/Counter Register Description Timer/Counter Control Register A– TCCR2A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2A is written when operating in PWM mode.
ATmega169V/L • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting.
• Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 65. Table 65. Clock Select Bit Description Timer/Counter Register – TCNT2 CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped).
ATmega169V/L Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal.
Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2A, and TCCR2A. 4.
ATmega169V/L • Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
Timer/Counter2 Interrupt Flag Register – TIFR2 Bit 7 6 5 4 3 2 1 0 – – – – – – OCF2A TOV2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega169V/L Figure 63. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169 and peripheral devices or between several AVR devices.
ATmega169V/L When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega169V/L The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega169V/L • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
ATmega169V/L Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 66 and Figure 67. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 67 and Table 68, as done below: Table 70.
USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
ATmega169V/L The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
Figure 69. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
ATmega169V/L Table 71.
Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 70. Synchronous Mode XCK Timing.
ATmega169V/L Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
ATmega169V/L Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega169V/L Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
ATmega169V/L Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.
The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
ATmega169V/L Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 72 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation.
ATmega169V/L Figure 74 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 74. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
Table 72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 73.
ATmega169V/L Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
USART Register Description USART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
ATmega169V/L • Bit 5 – UDRE: USART Data Register Empty The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
USART Control and Status Register B – UCSRB Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.
ATmega169V/L USART Control and Status Register C – UCSRC Bit 7 6 5 4 3 2 1 0 – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRC • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 74.
• Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 77. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only.
ATmega169V/L Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 79. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.
ATmega169V/L Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.
Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.
ATmega169V/L Universal Serial Interface – USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary.
ATmega169V/L The Three-wire mode timing is shown in Figure 77. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (data register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.
The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1<
ATmega169V/L Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 78.
Figure 79. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D P E F Referring to the timing diagram (Figure 79.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero.
ATmega169V/L Start Condition Detector The start condition detector is shown in Figure 80. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. USI Status Register – USISR Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USISR The Status Register contains interrupt flags, line status flags and the counter value.
ATmega169V/L Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by the counter. USI Control Register – USICR Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe.
Table 83. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 0 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega169V/L • Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer0 overflow clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option.
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega169V/L • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 41. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 86.
ATmega169V/L Analog to Digital Converter Features • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy TBD - 260 µs Conversion Time Up to TBD kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Seven Differential input channels Optional Left Adjustment for ADC Result Readout 0 - V CC ADC Input Voltage Range Selectable 1.
Figure 82. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega169V/L The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion.
conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
ATmega169V/L In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 87. Figure 85.
Figure 88. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update Table 87. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.
ATmega169V/L Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier.
ATmega169V/L Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 89. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2.
ATmega169V/L ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 91.
Figure 93. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 94.
ATmega169V/L ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 89 on page 204 and Table 90 on page 205). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Table 88. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + V REF 0x1FF 511 VADCm + 0.999 VREF 0x1FF 511 VADCm + 0.998 VREF 0x1FE 510 ... ... ... VADCm + 0.001 VREF 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF 0x3FF -1 ... ... ... VADCm - 0.999 VREF 0x201 -511 VADCm - VREF 0x200 -512 Example: ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ATmega169V/L • Bits 4:0 – MUX4:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 90 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 90. Input Channel Selections MUX4..
ADC Control and Status Register A – ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega169V/L • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 91.
• ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 203. ADC Control and Status Register B – ADCSRB Bit 7 6 5 4 3 2 1 0 ADHSM ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – ADHSM: ADC High Speed Mode Writing this bit to one enables the ADC High Speed mode.
ATmega169V/L LCD Controller The LCD Controller/driver is intended for monochrome passive liquid crystal display (LCD) with up to four common terminals and up to 25 segment terminals. Features • • • • • • • • • • Overview A simplified block diagram of the LCD Controller/Driver is shown in Figure 96. For the actual placement of I/O pins, refer to “Pinout ATmega169” on page 2.
Figure 96.
ATmega169V/L Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0 compared to none addressed COM lines. Non-energized segments are in phase with the addressed COM0, and energized segments have opposite phase and large amplitude. For waveform figures refer to “Mode of Operation” on page 211. Latched data from LCDDR3 - LCDDR0 is multiplexed into the decoder.
Figure 98. Driving a LCD with One Common Terminal VLCD VLCD SEG1 SEG0 GND GND VLCD VLCD COM0 COM0 GND GND VLCD GND SEG0 - COM0 SEG1 - COM0 GND -VLCD Frame 1/2 Duty and 1/2 Bias Frame Frame Frame For LCD with two common terminals (1/2 duty) a more complex waveform must be used to individually control segments. Although 1/3 bias can be selected 1/2 bias is most common for these displays. Waveform is shown in Figure 99.
ATmega169V/L 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is shown in Figure 100. SEG0 - COM0 is the voltage across a segment that is on and SEG0-COM1 is the voltage across a segment that is off. Figure 100.
Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can be selected by writing LCDAB to one. Low power waveform requires two subsequent frames with the same display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set every second frame. Default and low power waveform is shown in Figure 102 for 1/3 duty and 1/3 bias. For other selections of duty and bias, the effect is similar. Figure 102.
ATmega169V/L LCD Usage LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization process normally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but can also be adjusted during operation. Consider the following LCD as an example: Figure 103. LCD 2a 1b 2f 2b 2g 1c 2e 2c 51 50 COM2 COM1 COM0 2d 49 COM3 48 SEG0 47 ATmega169 SEG2 2f 2g ..
Assembly Code Example(1) LCD_Init: ; Use 32 kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1<
ATmega169V/L Before a re-initialization is done, the LCD controller/driver should be disabled Updating the LCD Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power waveform (LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no restrictions on writing these LCD Register locations, but an LCD data update may be split between two frames if data are latched while an update is in progress.
Assembly Code Example(1) LCD_disable: ; Wait until a new frame is started. Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; Set LCD Blanking and clear interrupt flag ; by writing a logical one to the flag. ldi r16, (1<
ATmega169V/L LCD Control and Status Register A – LCDCRA Bit 7 6 5 4 3 2 1 0 LCDEN LCDAB – LCDIF LCDIE – – LCDBL Read/Write R/W R/W R R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 LCDCRA • Bit 7 – LCDEN: LCD Enable Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned off immediately.
LCD Control and Status Register B – LCDCRB Bit 7 6 5 4 3 2 1 0 LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LCDCRB • Bit 7 – LCDCS: LCD Clock Select When this bit is written to zero, the system clock is used. When this bit is written to one, the external asynchronous clock source is used.
ATmega169V/L • Bits 2:0 – LCDPM2:0: LCD Port Mask The LCDPM2:0 bits determine the number of port pins to be used as segment drivers. The different selections are shown in Table 95. Unused pins can be used as ordinary port pins. Table 95.
• Bit 3 – Res: Reserved Bit This bit is reserved bit in the ATmega169 and will always read as zero. • Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0 The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are shown in Table 97. This Clock Divider gives extra flexibility in frame rate selection. Table 97. LCD Clock Divide LCDCD2 LCDCD1 LCDCD0 Output from Prescaler Divided by: 0 0 0 1 256 Hz 0 0 1 2 128 Hz 0 1 0 3 85.
ATmega169V/L LCD Contrast Control Register – LCDCCR Bit 7 6 5 4 3 2 1 0 – – – – LCDCC3 LCDCC2 LCDCC1 LCDCC0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LCDCCR • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega169 and will always read as zero. • Bits 3:0 – LCDCC3:0: LCD Contrast Control The LCDCC3:0 bits determine the maximum voltage VLCD on segment and common pins. The different selections are shown in Table 99.
LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visible). Unused LCD Memory bits for the actual display can be used freely as storage.
ATmega169V/L JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this fuse programmed.
ATmega169V/L Figure 105. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected data register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK.
ATmega169V/L A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 229. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the Onchip debug system to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or LB2 Lock bits are set.
On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 MSB/IDRD 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega169V/L IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 106 shows the structure of the Device Identification Register. Figure 106.
ATmega169V/L Reset Register The Reset Register is a test data register used to reset the part. Since the AVR tri-states Port Pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register.
EXTEST; 0x0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain.
ATmega169V/L Boundary-scan Related Register in I/O Memory MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
Figure 108. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
ATmega169V/L Figure 109.
Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 111 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
ATmega169V/L Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 112. The Boundary-scan cell from Figure 113 is attached to each of these signals. The signals are described in Table 104. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 112. Analog Comparator BANDGAP REFERENCE ACBG ACD ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 113.
Table 104.
ATmega169V/L Table 105.
Table 105. Boundary-scan Signals for the ADC (1) (Continued) 242 Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC Enable 10x gain 0 0 Input Enable 20x gain 0 0 GNDEN Input Ground the negative input to comparator when true 0 0 HOLD Input Sample & Hold signal. Sample analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high.
ATmega169V/L Table 105. Boundary-scan Signals for the ADC (1) (Continued) Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC Signal Name Direction as Seen from the ADC SCTEST Input Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4 0 0 ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high.
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. 1024 ⋅ 1.5V ⋅ 0,95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1.5V ⋅ 1.05 ⁄ 5V = 323 = 0x143 The lower limit is: The upper limit is: The recommended values from Table 105 are used unless other values are given in the algorithm in Table 106. Only the DAC and port pin values of the Scan Chain are shown.
ATmega169V/L ATmega169 Boundaryscan Order Table 107 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Table 107. ATmega169 Boundary-scan Order (Continued) 246 Bit Number Signal Name Module 168 MUXEN_3 ADC 167 MUXEN_2 166 MUXEN_1 165 MUXEN_0 164 NEGSEL_2 163 NEGSEL_1 162 NEGSEL_0 161 PASSEN 160 PRECH 159 ST 158 VCCREN 157 PE0.Data 156 PE0.Control 155 PE0.Pullup_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pullup_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pullup_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pullup_Enable 145 PE4.Data 144 PE4.
ATmega169V/L Table 107. ATmega169 Boundary-scan Order (Continued) Bit Number Signal Name Module 132 PB0.Control Port B 131 PB0.Pullup_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pullup_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pullup_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pullup_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pullup_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pullup_Enable 115 PB6.Data 114 PB6.Control 113 PB6.Pullup_Enable 112 PB7.
Table 107. ATmega169 Boundary-scan Order (Continued) 248 Bit Number Signal Name Module 96 EXTCLK (XTAL1) 95 OSCCK Clock input and Osillators for the main clock (Observe-only) 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pullup_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pullup_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pullup_Enable 77 PD5.Data 76 PD5.
ATmega169V/L Table 107. ATmega169 Boundary-scan Order (Continued) Bit Number Signal Name Module 60 PC0.Pullup_Enable Port C 59 PC1.Data 58 PC1.Control 57 PC1.Pullup_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pullup_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pullup_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pullup_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pullup_Enable 41 PC7.Data 40 PC7.Control 39 PC7.
Table 107. ATmega169 Boundary-scan Order (Continued) Boundary-scan Description Language Files 250 Bit Number Signal Name Module 24 PA4.Pullup_Enable Port A 23 PA3.Data 22 PA3.Control 21 PA3.Pullup_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pullup_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pullup_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pullup_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pullup_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pullup_Enable 5 PF1.Data 4 PF1.
ATmega169V/L Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
ATmega169V/L Figure 115. Read-While-Write vs.
Figure 116.
ATmega169V/L Table 109. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega169V/L • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
Figure 117. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: Self-Programming the Flash 1. The different variables used in Figure 117 are listed in Table 115 on page 264. The program memory is updated in a page by page fashion.
ATmega169V/L Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega169V/L When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 118 on page 266 for detailed description and mapping of the Extended Fuse byte.
Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega169V/L ret ; re-enable the RWW section ldi spmcrval, (1<
Table 115. Explanation of different variables used in Figure 117 and the mapping to the Z-pointer(1) Corresponding Z-value Variable PCMSB 12 Most significant bit in the Program Counter. (The Program Counter is 13 bits PC[12:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires six bits PC [5:0]). ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega169V/L Memory Programming Program And Data Memory Lock Bits The ATmega169 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 117. The Lock bits can only be erased to “1” with the Chip Erase command. Table 116.
Table 117. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
ATmega169V/L Table 119. Fuse High Byte Fuse High Byte Bit No OCDEN(4) 7 JTAGEN 6 SPIEN(1) Description Default Value Enable OCD 1 (unprogrammed, OCD disabled) Enable JTAG 0 (programmed, JTAG enabled) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked.
ATmega169V/L Table 121. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1 (“0” selects low byte, “1” selects high byte). XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load.
Table 124. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Table 125. No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD No.
ATmega169V/L Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 122 on page 269 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5.
1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3.
ATmega169V/L Figure 119. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 125 on page 270. Figure 120. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 121 for signal waveforms). Figure 121. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR.
ATmega169V/L Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 271 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 271 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, BS2 to “1”, and BS1 to “0”.
ATmega169V/L Parallel Programming Characteristics Figure 1 24. Parallel Pro grammin g Timing , Inclu din g some Gene ral Timin g Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 12 5.
Figure 126. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 124 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 128.
ATmega169V/L Table 128. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Serial Downloading Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
Serial Programming Algorithm When writing serial data to the ATmega169, data is clocked on the rising edge of SCK. When reading data from the ATmega169, data is clocked on the falling edge of SCK. See Figure 128, Figure 129 and Table 131 for timing details. To program and verify the ATmega169 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 130): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
ATmega169V/L Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
Table 130. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Write EEPROM Memory 1100 0000 000x xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page.
ATmega169V/L Serial Programming Characteristics Figure 129. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 131. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATmega169L) tCLCL Oscillator Period (ATmega169L) Typ 0 Max Units 8 MHz 125 ns Oscillator Frequency (ATmega169, VCC = 4.5V 5.5V) 0 tCLCL Oscillator Period (ATmega169, VCC = 4.5V 5.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 130. Figure 130.
ATmega169V/L PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) PROG_PAGEREAD (0x7) Data Registers The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the data register.
Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega169V/L Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 132. The state sequence when shifting in the programming commands is illustrated in Figure 133. Figure 132.
Table 132. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega169V/L Table 132. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
Table 132. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
ATmega169V/L Figure 133.
including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 134. Flash Data Byte Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK.
ATmega169V/L Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4. Load address Low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8.
gram counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. Programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5.
ATmega169V/L Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2.
Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC +0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega169V/L DC Characteristics TA = -40°C to 85°C, VCC = 1.8V to 3.6V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 3V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 3V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 1.8V VCC = 2.7V Note: Min. Typ. TBD TBD TBD Max. Units TBD mV TBD nA ns 1. “Max” means the highest value where the pin is guaranteed to be read as low 2.
External Clock Drive Waveforms Figure 135. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 133. External Clock Drive VCC = 1.8 - 3.6V SPI Timing Characteristics 298 VCC = 2.7 - 3.6V Min. Max. Min. Max.
ATmega169V/L Figure 136. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 137. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) MSB ...
ADC Characteristics – Preliminary Data Table 135.
ATmega169V/L ATmega169 Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved – – – – – – – – Page (0xFE) LCDDR18 – – – – – – – SEG24 223 (0xFD) LCDDR17 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 223 (0xFC) LCDDR16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 223 (0xFB) LCDDR15 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 223 (0xFA) Reserved – – – – – – – – (0xF9) LCDDR13 – – – – – – – SEG24 223 (0xF8) LC
ATmega169V/L Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved – – – – – – – – (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) USIDR (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 184 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 185 (0xB7) Reserved – – – – – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7D) Reserved – – – – – – – – ADLAR MUX4 MUX3 Page (0x7C) ADMUX REFS1 REFS0 (0x7B) ADCSRB ADHSM ACME (0x7A) ADCSRA ADEN ADSC (0x79) ADCH ADC Data Register High byte 207 (0x78) ADCL ADC Data Register Low byte 207 ADATE ADIF ADIE MUX2 MUX1 MUX0 ADTS2 ADTS1 ADTS0 204 208 ADPS2 ADPS1 ADPS0 206 (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved
ATmega169V/L Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) Reserved – – – – – – – – Page 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 140 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 122 0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 91 0x14 (0x34) PORTG – – PORTG5 PORTG4 PORTG3 PORTG2 PO
Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers
ATmega169V/L Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ←
Mnemonics POP Operands Rd Description Pop Register from Stack Operation Rd ← STACK Flags #Clocks None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega169V/L Ordering Information Speed (MHz) Power Supply 1 1.8 - 3.6V 4 Note: 2.7 - 3.6V Ordering Code Package ATmega169V-1AC 64A Operation Range Commercial (0°C to 70°C) ATmega169V-1AI 64A Industrial (-40°C to 85°C) ATmega169L-4AC 64A Commercial (0°C to 70°C) ATmega169L-4AI 64A Industrial (-40°C to 85°C) This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Packaging Information 64A 64-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP), 14x14mm body, 2.0mm footprint, 0.8mm pitch. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-026 AEB 16.25(0.640) SQ 15.75(0.620) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC 14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.09(0.004) 1.20 (0.047) MAX 0˚~7˚ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002 ) *Controlliing dimension: millimeter REV.
ATmega169V/L Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Disclaimer ............................................................................................................. 2 Overview................................................................................................ 3 Block Diagram ..........................
System Control and Reset ................................................................. 36 Internal Voltage Reference ................................................................................. 41 Watchdog Timer ................................................................................................. 42 Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 44 Interrupts .............................................................................................
ATmega169V/L Modes of Operation .......................................................................................... Timer/Counter Timing Diagrams....................................................................... 8-bit Timer/Counter Register Description ......................................................... Asynchronous operation of the Timer/Counter ................................................. Timer/Counter Prescaler........................................................................
JTAG Interface and On-chip Debug System .................................. 225 Overview ........................................................................................................... Test Access Port – TAP.................................................................................... TAP Controller .................................................................................................. Using the Boundary-scan Chain .................................................................
ATmega169V/L ADC Characteristics – Preliminary Data........................................................... 300 LCD Controller Characteristics – Preliminary Data........................................... 300 ATmega169 Typical Characteristics – Preliminary Data............... 301 Register Summary ............................................................................ 302 Instruction Set Summary ................................................................. 306 Ordering Information...............
vi ATmega169V/L 2514A–AVR–08/02
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